Tracking Re-Use Of Design IPs

By Amit Varde - 24 Feb, 2020 - Comments: 0

Design teams have a great incentive to create design blocks or IPs that can be reused: Each time an IP is successfully reused, precious time is saved from project schedule. Of course, as easy as it sounds, achieving this goal in real life is not simple. In reality, the observation is that design libraries cannot be used as-is by multiple projects. Consider this scenario: A smart new graduate... » read more

What’s In Your IP?

By Ed Sperling - 21 Feb, 2020 - Comments: 0

Jeff Markham, software architect at ClioSoft, talks with Semiconductor Engineering about IP traceability in markets such as automotive and aerospace, what’s actually in IP, what should not be in that IP from a security standpoint, and how all of this data can used to avert system reliability issues in the future. » read more

Big Design, IP and End Market Shifts In 2020

By Brian Bailey - 30 Jan, 2020 - Comments: 0

EDA is on a roll. Design starts are up significantly thanks to increased investment in areas such as AI, a plethora of new communications standards, buildout of the Cloud, the race toward autonomous driving and continued advancements in mobile phones. Many designs demand the latest technologies and push the limits of complexity. Low power is becoming more than just reducing wasted power at t... » read more

Network Storage Optimization In Chip Design

By Ed Sperling - 21 Jan, 2020 - Comments: 0

Prathna Sekar, technical account manager at ClioSoft, explains how to manage large quantities of data, how this can quickly spin out of control as colleagues check in data during the design process, and how to reduce the amount that needs to be stored. » read more

Moore’s Law, Supply Chains And Security

By Brian Bailey - 16 Jan, 2020 - Comments: 0

The debate about the future of Moore's Law continues, while other parts of the industry look for alternatives. In between, supply chains are being pulled in multiple directions, with safety and security often in the middle. All across the semiconductor industry, significant changes are underway. Some of these have been in the works for some time. Others are new or accelerating faster than an... » read more

Auto Industry Shifts Gears On Where Data Gets Processed

By Ann Mutschler - 09 Jan, 2020 - Comments: 0

In-vehicle processing is becoming a major challenge in automotive electronics due to the massive amount of data being generated by sensors — especially cameras — and the rapid response time required to avoid accidents. The initial idea that all data could be sent to the cloud for processing has been shelved, most likely permanently. In its place is a growing recognition that data needs t... » read more

Can You Afford To Waste Time On Your Next Design Project?

By Amit Varde - 09 Jan, 2020 - Comments: 0

Let’s be honest: engineers are asked to perform miracles every day, and they almost always deliver. They are challenged to invent the future in the form of newly sophisticated, powerful and highly functional systems-on-chips and systems. On top of this, they’re required to do so with an increasingly complex array of tools and re-use increasing amounts of IP to speed time-to-market. Oh, and ... » read more

Challenges In IP Reuse

By Ed Sperling - 09 Dec, 2019 - Comments: 0

Jeff Markham, software architect at ClioSoft, explains why IP reuse is so important in advanced process node SoC chip designs, what companies need to keep track of when working with third-party IP, and how it needs to be characterized. » read more

Thoroughly Verifying Complex SoCs

By Ann Mutschler - 26 Nov, 2019 - Comments: 0

The number of things that can go wrong in complex SoCs targeted at leading-edge applications is staggering, and there is no indication that verifying these chips will function as expected is going to get any easier. Heterogeneous designs developed for leading-edge applications, such as 5G, IoT, automotive and AI, are now complex systems in their own right. But they also need to work in conju... » read more

Managing Analog Designs For Successful Tapeouts

By Cliosoft - 06 Nov, 2019 - Comments: 0

Managing analog designs beyond data management to IP reuse and beyond in order to create a collaborative platform for design management from concept-to-GDSII. Click here to read more. » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

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Partitioning In The Chiplet Era

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3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

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AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

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What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

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