Front End Comes To The Back End

By Jeff Chappell - 19 Sep, 2013 - Comments: 0

By Jeff Chappell For outsourced assembly and test (OSAT) houses either planning for or already offering through-silicon via (TSV) capability for their 3D packaging efforts, this has meant the front end is coming to the back end, in a manner of speaking. A bit of an exaggeration perhaps, as most generalizations are. But thanks to TSVs, in a very real sense some of what would typically be the... » read more

Semiconductor Fab Materials Outlook

By SEMI - 16 Aug, 2013 - Comments: 0

By Dan Tracy While segments of the global economy are slowing and uncertainty is once again on the rise, fundamental unit trends for semiconductor materials have improved in recent months and growth expectations for the fab materials market remain modest for 2012 and into 2013. Three-month shipment data shows silicon shipments—from the wafer suppliers to the fabs—during the current cycl... » read more

SPOTLIGHT ON FD-SOI, FINFETS AT IEEE SOI CONFERENCE ;1-4 OCT, NAPA

By Various Writers - 25 Sep, 2012 - Comments: 0

The 38th annual SOI Conference is coming right up. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications. Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the ... » read more

Challenges Mount For Interconnect

By Mark LaPedus - 26 Jun, 2012 - Comments: 0

By Mark LaPedus There are a plethora of chip-manufacturing challenges for the 20nm node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect. The problems with lithography are well documented.... » read more

CMP, ST et al offer 28nm FD-SOI for prototyping, research

By Various Writers - 06 Nov, 2011 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~ ~ What would a port to 28nm FD-SOI do for your design? A recent announcement by CMP, STMicroelectronics and Soitec invites you to find out. Specifically, ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process – which uses innovative silicon substrates from Soitec and incorporates robust, compact model... » read more

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tag: CMP

Front End Comes To The Back End

Semiconductor Fab Materials Outlook

SPOTLIGHT ON FD-SOI, FINFETS AT IEEE SOI CONFERENCE ;1-4 OCT, NAPA

Challenges Mount For Interconnect

CMP, ST et al offer 28nm FD-SOI for prototyping, research