Challenges Mount For Interconnect

Back end of the line changes are being planned, but nothing is happening quickly; resistance capacitance continues to rise at each new process node.


By Mark LaPedus
There are a plethora of chip-manufacturing challenges for the 20nm node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect.

The problems with lithography are well documented. Chipmakers have extended optical lithography far below the wavelength of a given technology, forcing them to play difficult tricks with photons to enable higher resolutions and finer pitches. And, of course, extreme ultraviolet lithography (EUV) remains delayed.

What isn’t so obvious are the mounting challenges associated with interconnects. Interconnects—those tiny wiring schemes in devices—are becoming more compact at each node, causing a degradation in performance and an increase in resistance. The big concern is latency or resistance-capacitance (RC) in a device, Patton said. “The RC is going up,” he said.

The resistivity problems in planar devices have fueled the development of stacked 3D chips using through-silicon vias (TSVs), whether those TSVs run through a die or a separate interposer die in so-called 2.5D chips. In either case, stacking is a viable way to circumvent the RC problems, but advanced chip-stacking has a multitude of challenges and is still a few years away from mass production.

So for the short-term the industry is stuck with planar and must make advances on two interconnect fronts: metallization and low-k dielectrics. In metallization, there is a potential sea of change taking place in advanced designs. Physical-vapor deposition (PVD), the workhorse tool technology for the metallization process, continues to extend to finer geometries. At 14nm and beyond, the industry is now looking at rival tool technologies like chemical-vapor deposition (CVD) and atomic-layer deposition (ALD). On top of that, new materials are also emerging.

In the low-k part of the equation, the technology is moving at a snail’s pace and remains stuck amid a slew of challenges. And air gaps, the ultimate solution for the interlayer dielectric (ILD), appears to have been delayed or abandoned for logic designs.

Changes in the interconnect
The formation of the interconnect takes place at the back-end-of-the-line (BEOL) and generally involves a copper damascene process. In this process, a structure undergoes a diffusion barrier etch step. Then, a via dielectric is deposited. An etch step then forms a gap, where the lines and vias are formed.

Then, a thin layer of barrier of tantalum (Ta) and tantalum nitride (TaN) materials are deposited using PVD. Ta is used to form the liner and TaN is for the barrier in a structure. The barrier layer is coated over by a copper (Cu) seed barrier via PVD. And finally, the structure is electroplated with copper and ground flat using chemical mechanical polishing (CMP).

For years, the industry has been talking about the demise of PVD, prompting the need for ALD. PVD is a deposition method that involves high-temperature vacuum evaporation and sputtering. ALD deposits conformal thin-films one atom at a time, but the technology is slower.

“Scaling PVD below 30nm is challenging,” said Mike Mayberry, vice president and director of components research in the Technology and Manufacturing Group at Intel, at the recent International Interconnect Technology Conference (IITC) in San Jose, Calif. “Looking forward, new methods are required to fabricate thin conformal liners which do not consume substantial volume. These may include ALD or other methods which allow high surface migration to deliver conformal films.”

But defying the odds, PVD continues to have legs. “PVD has been the technology of choice” due to cost and reliability, said Kevin Moraes, director of global product management within the Metal Deposition Product Business Group at Applied Materials. “Even at 14nm, the industry is pushing PVD to work with Ta and TaN. 10nm is still open.”

At 14nm, a tool technology must be capable of depositing both the barrier and liner layers at less than 15 angstroms. To handle those capabilities for even 20nm and beyond, the industry is evaluating ALD and CVD as a possible replacement for PVD in some steps. “The challenge with ALD and CVD is to match the barrier properties,” as compared to those of PVD, said Kavita Shah, product manager for metal deposition products at Applied.

To complicate matters, the industry is also looking at various options that involve new materials. The most obvious and cost-effective choice is using PVD for depositing both Ta and TaN, said Sree Kesapragada, global product manager for metal deposition products at Applied.

A second option is using PVD for the TaN barrier layer and CVD for two possible new replacement materials for the Ta liner: cobalt (Co) and ruthenium (Ru), he said. A third possibility is using ALD for the TaN barrier layer and PVD for the Ta liner. And a longer-term solution is ALD for the TaN barrier layer and CVD for the Co or Ru liner, he said.

Daniel Edelstein, an IBM Fellow and manager of BEOL technology strategy at IBM, said there are various tradeoffs with next-generation tools and materials. “ALD supposedly offers better control of thinner films down to the atomic layer, but in some cases CVD is as good, and may produce higher-purity films. Both have exceptional step coverage to coat high aspect ratio tall/narrow features. But it’s a case-by-case basis as to which (tool technology) has a better process for a particular material. Ru shows the best wettability for Cu seed layer or direct plating. Co is second best. Ru is extremely difficult to polish by CMP. Co is easy. Ru is a poor Cu and O2 diffusion barrier. Co is a decent Cu barrier, but not a perfect O2 barrier.”

There are other issues, too. As interconnect feature sizes continue to shrink, electromigration (EM) lifetimes drop. At IITC, Applied Materials and IBM presented a paper that could solve the problem. Cobalt films with various thicknesses were selectively deposited as copper capping layers by CVD. As a result, EM lifetime enhancement was achieved from the in-situ capping process, according to the paper.

Low-k woes
It’s a completely different story for low-k. For years, leading-edge designs used silicon-dioxide materials for the ILD, which have “k” values ranging from 3.9 to 4.2. Then, at 130nm, the industry inserted fluorosilicate glass (FSG) materials for the ILD, which had a dielectric constant of 3.6.

But at 90nm, chipmakers struggled to migrate to low-k materials like carbon-doped oxide, which were supposed to lower the “k” value to about 2.7 or so. Low-k materials reduce capacitance and propagation delays, but as it turned out, these films suffer from poor mechanical properties and are prone to potential damage in the CMP process.

Consequently, the industry’s roadmap for low-k processes stalled. In 1999, the ITRS roadmap called for dielectric constant values of 2.7 to 2.2 by 2005. But today, leading-edge chipmakers are using low-k materials with constant values at 2.5 or 2.55, said IBM’s Edelstein. “The ability to extend the dielectric gets harder and harder,” he said.

At one time, logic vendors hoped to use air or a vacuum gap for the ILD, which could bring the k-value down to its theoretical limit of 1.0. But air gap technology was more difficult and expensive than previously thought, forcing logic vendors to delay the idea.

So in the near term, the industry hopes to push low-k down to 2.3 to 2.0. At IITC, ASM International described an approach to enable films down to 2.0. Porous SiOCH films at 2.0 were deposited with siloxane and porogen precursors by plasma-enhanced CVD. The films were treated by UV cure to remove porogen and to enhance mechanical strength. The porosity and average pore diameter were 42% and 3.3nm, respectively, according to the company.

IBM provided more details about its post porosity plasma protection (P4) process, which reduces film damage and enables k values to 2.0. In P4, porosity is protected with organic polymers as filler materials. In another effort using organic materials, IMEC and Sumitomo described a spin-on and non-porogen scheme that enables low-k films at 2.3.