tag: RC

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification
By Greg Curtis - 25 Jun, 2020 - Comments: 0

My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers of our design to generate the design for manufacturing of the chip. We proactively worked to mitigate cross coupling of noise to our signal nets, but we were rarely concerned about interconnect re... » read more

Boosting Analog Reliability
By Ed Sperling - 17 Jan, 2019 - Comments: 0

Aveek Sarkar, vice president of Synopsys’ Custom Compiler Group, talks about challenges with complex design rules, rigid design methodologies, and the gap between pre-layout and post-layout simulation at finFET nodes. https://youtu.be/JRYlYJ31LLw » read more

All About Interconnects
By Larry Zhao - 18 Dec, 2017 - Comments: 1

It's well known that advanced chips contain billions of transistors – this is an incredible, mind-blowing fact to be sure – but did you know that large-scale integrated chips (about the size of a fingernail) can contain ~30 miles of interconnect “wires” in stacked levels? These wires function like highways or pipelines to transport electrons, connect transistors and other components to ... » read more

Cobalt To The Rescue
By Mark LaPedus - 13 May, 2014 - Comments: 0

A big concern for chipmakers is a key part of the manufacturing flow—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within a device. Interconnects, those tiny wiring schemes in devices, are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the dreaded resistance-capacitance (RC) ... » read more

Challenges Mount For Interconnect
By Mark LaPedus - 26 Jun, 2012 - Comments: 0

By Mark LaPedus There are a plethora of chip-manufacturing challenges for the 20nm node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect. The problems with lithography are well documented.... » read more

Bucket Lists
By Ed Sperling - 26 Jun, 2012 - Comments: 0

At 130nm, the introduction of copper interconnects, 300mm wafers and low-k dielectrics left the entire supply chain breathless. There had never been as many changes at a single process node in the history of semiconductors. At 28nm, the number of changes will pale compared to what’s necessary at 20nm, and that will pale to what’s required at 14nm. But unlike 130nm, when most of those cha... » read more

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