Post Layout Simulation Is Becoming The Bottleneck For Analog Verification

My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers of our design to generate the design for manufacturing of the chip. We proactively worked to mitigate cross coupling of noise to our signal nets, but we were rarely concerned about interconnect resistance affecting the performance of our designs.

Fast forward many years later, and today, the rapid growth in data expansion is driving an explosion in new designs and new requirements for high performance computing, mobile, automotive, and Internet of Things (IoT) applications. This in turn is driving a push to smaller process geometries to address performance, size, and cost.

This continued scaling of complex designs into the 16nm technology node and below is critical for today’s applications. At the 16nm technology node, the emergence and use of the FinFET 3D transistor, as compared to planar technology, brings many new opportunities to design, but it also introduces new challenges to analog verification.

FinFET transistor technology addresses the performance versus power tradeoff consideration. Designers can run the transistors faster and use the same amount of power, as compared to the planar equivalent in larger process geometries, or run them at the same performance using less power. This provides design teams the ability to balance the performance and power curve to match the needs of each application.

As with many previous process geometry migrations, new opportunities also present new design and verification challenges. One of those challenges is a significant increase in interconnect resistance and distributed resistance and capacitance parasitics. The extraction of parasitics provides a more accurate analog model of the design, so that the simulations can more accurately represent the analog circuit response. Simply simulating the schematic design is no longer adequate¹ and attempting to simulate a large post layout design is becoming the bottleneck for analog verification.

Nanometer circuit verification challenges
There are many benefits to migrating to smaller process geometries, such as, number of transistors/area, lower power, and higher performance. However, these benefits can be easily negated if the simulation technology cannot keep up with these new challenges, causing design schedules to slip and therefore missing the time to market window.

In addition to fast and efficient simulation technology, fast and accurate resistor/capacitor (RC) extraction is becoming increasingly important. At lower geometries, interconnect resistance is becoming an increasing percentage of the total path resistance. From 40nm to 7nm, the relative wire resistance has risen more than six fold and the subsequent RC netlist can increase the circuit simulation time by several orders of magnitude¹, adding to the simulation burden.

There are three aspects to the evolution of high-performance, high-capacity, and high-accuracy SPICE circuit simulation technology: device model equations, matrix evaluation, and time-step control.

For device model equations, with each generation of BSIM device models, there is a significant increase in the number of equations to solve per transistor and the FinFET 3D structure (Figure 1) has driven an explosion in the number of computations required per device. This contributes to more expensive model evaluation and longer simulation times.

For matrix evaluation there are two problems, matrix factor and matrix solve. Matrix factor is the key computation and continual improvements have been critical to address nanometer circuit simulations challenges. The move to FinFET devices has driven an increase in the number and complexity of parasitic elements, creating very large, dense matrices to be evaluated at each time-step.

Lastly, for time-step control, solutions have been based on heuristics evolving over the past four decades and time-step fidelity is critical to ensure SPICE accuracy.

Figure 1. FinFET 3D Structure

Device noise effects that were once a second or third order effect become a first order effect in complex nanometer CMOS circuits that have tight specifications, especially those with low voltages or noise-sensitive architectures. Including device noise is no longer optional. What used to work at older process nodes with sufficient experience, intuition, and iterations no longer apply, especially at 16nm and below. As an example, there is a ~30dB difference in the closed loop PLL phase noise (Figure 2) with and without device noise effects.

Figure 2. Closed Loop PLL Phase Noise

Other contributing factors than can effect design verification are complex power network circuitry techniques, such as power gating to reduce leakage currents, read/write assist circuits to increase operating efficiency, stability, and improving static noise margins. Also, these complex power management circuits that use multiple operating voltages can cause on chip variations that increase the number of corner simulations (Figure 3) required for adequate design verification and increase sensitivity to voltage drop, reducing noise margin.

Figure 3. Typical Number of PVT Corners by Process Geometry

At smaller process geometries, an exponential increase of much more complex parasitic RCs and coupling capacitance (Figure 4) due to the 3D transistor architecture and local interconnects and trench contacts can greatly impact the ability to verify the design in a timely fashion. Significant effects of interconnect parasitics include: signal delay, signal noise, and IR drop.

Figure 4. Parasitic Complexity vs Process Geometry

As CMOS scaling extends to the most advanced geometries, designers need to be aware that device behavior depends not only on traditional geometric parameters, such as channel length and width, but also on layout implementation details of the device and its surroundings. Due to intentional stress applied to a device to improve performance, a large number of transistor instance-based parameters increase, impacting the simulation performance through longer parameter and model evaluation time, and less sharing of transistor models.

Nanometer circuit verification with the Analog FastSPICE (AFS) platform
The AFS platform continues to advance the state of the art in SPICE simulation technology with new algorithms, optimization, and reduction techniques to address the evolving challenges at nanometer process geometries.

In comparison to the BSIM4 model, the Berkeley Short-channel IGFET Model for Common Multi-Gate (BSIM-CMG) is much more complicated (Figure 5) for both the model equation and topology. Because of this complexity, the model evaluation can be 2X slower than the BSIM4 model. The AFS simulator has been optimized and verified for accuracy and performance, and provides a similar memory footprint as the BSIM4 model.

Figure 5. BSIM-CMG Model

Due to the significant increase in extracted parasitic RCs and coupling capacitance, the AFS simulator employs advanced RC reduction and adaptive matrix optimization techniques to maintain simulator performance and accuracy.

The Analog FastSPICE platform provides the world’s fastest nanometer circuit verification and is ideally suited for verifying the most advanced nanometer circuits. With a proven greater than 120 dB dynamic range, it is 5-10X faster than any other SPICE accurate simulator on a single core. For long runs, AFS employs multithreading for scalable performance improvements. The device noise analysis delivers silicon-accurate results with numerous customer testimonials citing simulated results within 1-2 dB of measured silicon. Lastly, with its greater than 100M element capacity, AFS enables verification of full circuits with detailed parasitics for the most advanced process geometries, removing the analog verification bottleneck caused by the exponential increase in interconnect resistance and distributed resistance and capacitance parasitics with no accuracy loss.

Summary
The rapid growth in data expansion is driving an explosion in new designs and new requirements for high performance computing, mobile, automotive, and Internet of Things (IoT) applications. This in turn is driving a push to smaller process geometries to address performance, size, and cost.

As with many previous process geometry migrations, new opportunities also present new design challenges. One of those challenges is a significant increase in interconnect resistance and distributed resistance and capacitance parasitics. Attempting to simulate a large post layout design is becoming the bottleneck for analog verification.

For challenging nanometer circuit verification, the Analog FastSPICE platform delivers the most accurate, most comprehensive, and highest-performance verification capabilities available in a single-executable platform and is foundry certified accurate by the world’s leading foundries at the most advanced process geometries, removing the analog verification bottleneck.

Reference
[1] https://www.siliconcr.com/resource/detail/25/high-performance-pll-design-in-tsmc-5nm-finfet-process-