Cobalt To The Rescue

Looming interconnect issues eased by new material introduction at 20nm and below.

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A big concern for chipmakers is a key part of the manufacturing flow—the backend-of-the-line (BEOL).

In chip production, the BEOL is where the interconnects are formed within a device. Interconnects, those tiny wiring schemes in devices, are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the dreaded resistance-capacitance (RC) delay in chips.

RC delay has been the topic of concern for years, but the problems won’t go away. In fact, they’re getting worse at the 20nm node and beyond.

To solve part of the problem, Applied Materials announced its Endura Volta CVD Cobalt system. The two enabling applications in the system, a conformal cobalt liner and a selective cobalt capping layer, provide complete enclosure of the copper lines, improving reliability by an order of magnitude.

The introduction of cobalt as a metal encapsulation film marks the most significant materials change to the interconnect in over 15 years, said Kavita Shah, global product manager at Applied Materials.

“When we go down to 20nm, we are just running out of room. There is no way to build any redundancy from the design aspect. What this means is that even if a few of these structures are not filled properly, the yield impact starts to become pretty dramatic,” she said.

At 20nm and beyond, the industry will need to make changes in the flow. “In today’s interconnects, we start to see other challenges, such as high current densities. As this current density goes up, other secondary electrical effects start to dominate,” Shah said. “In order to address the electrical aspects of interconnect technology, we are beginning to see the need for new materials.”

The Endura Volta CVD system consists of two new process steps. The first step involves the deposition of a thin, conformal CVD cobalt liner to increase the gap fill window of copper in narrow interconnects. This process improves the performance and yield of the device by integrating the pre-clean, PVD barrier, CVD cobalt liner and copper seed processes under ultra-high vacuum on the same platform.

The second step, a new “selective” CVD cobalt capping step, is deposited after CMP to encapsulate the copper lines for enhanced reliability performance. Complete envelopment of copper lines with cobalt creates an engineered interface that demonstrates over 80x improvement in device reliability.

“Applied’s unique CVD cobalt processes represent an innovative materials-enabled scaling solution,” said Sundar Ramamurthy, vice president and general manager of Metal Deposition Products at Applied Materials. “It is deeply satisfying that these materials and process innovations in development for almost a decade are now being adopted by our customers for their high-performance mobile and server chips.”