RISC-V Profiles Help Conformance

By Brian Bailey - 18 Dec, 2024 - Comments: 0

Experts At The Table: What's needed to be able to trust that a RISC-V implementation will work as expected across multiple designs using standard OSes. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO of Codasip; Neil Hand, director of marketing at Siemens EDA (at the time of this discussion); Frank Schirrmeist... » read more

RISC-V’s Software Portability Challenge

By Brian Bailey - 13 Nov, 2024 - Comments: 0

Experts At The Table: RISC-V provides a platform for customization, but verifying those changes remains challenging. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO of Codasip; Neil Hand, director of marketing at Siemens EDA (at the time of this discussion); Frank Schirrmeister, executive director for strategi... » read more

RISC-V Conformance

By Brian Bailey - 31 Oct, 2024 - Comments: 0

Experts At The Table: Despite growing excitement and participation in the development of the RISC-V ecosystem, significant holes remain in the development flow. One of the most concerning is conformance, which must exist before software portability becomes possible. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO... » read more

Chip Industry Week In Review

By The SE Staff - 21 Jun, 2024 - Comments: 0

BAE Systems and GlobalFoundries are teaming up to strengthen the supply of chips for national security programs, aligning technology roadmaps and collaborating on innovation and manufacturing. Focus areas include advanced packaging, GaN-on-silicon chips, silicon photonics, and advanced technology process development. Onsemi plans to build a $2 billion silicon carbide production plant in the ... » read more

Blog Review: November 15

By Jesse Allen - 15 Nov, 2023 - Comments: 0

Cadence's Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4. Synopsys' Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models. Siem... » read more

Blog Review: Nov. 8

By Jesse Allen - 08 Nov, 2023 - Comments: 0

Siemens' Todd Westerhoff takes a look at the three stages of power integrity analysis for PCBs, challenges to board-level signal integrity, and best practices for getting the most accurate estimate of design performance. Synopsys' William Ruby provides a brief overview of the evolution of low-power design techniques and finds opportunities to reduce power and to make chip designs more energy... » read more

Coding And Debugging RISC-V

By Ann Mutschler - 06 Nov, 2023 - Comments: 0

As monolithic device scaling continues to wind down and evolve toward increasingly heterogeneous designs, it has created an inflection point for chip architects to create customized cores that are much more energy efficient and faster than off-the-shelf processors. Zdeněk Přikryl, CTO of Codasip, talks about where RISC-V fits into this picture, using a modular ISA and custom instruction layer... » read more

Chip Industry Week In Review

By The SE Staff - 03 Nov, 2023 - Comments: 0

By Susan Rambo, Gregory Haley, Jesse Allen, and Liz Allan President Biden issued an executive order on the “Safe, Secure, and Trustworthy Development and Use of Artificial Intelligence.” It says entities need to report large-scale computing clusters and the total computing power available, including “any model that was trained using a quantity of computing power greater than 1,026 inte... » read more

Causes Of Memory Unsafety

By Roddy Urquhart - 26 Oct, 2023 - Comments: 0

Memory unsafety is a characteristic of many of today’s systems. The root cause of buffer bounds vulnerabilities such as buffer overflows and over-reads is unsafe programming. Major software vendors consistently report memory unsafety problems. For example, the Chromium open-source browser project has stated that 69% of CVEs (Common Vulnerabilities and Exposures) reported relate to memory... » read more

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