Re-Targetable LLVM C/C++ Compiler For RISC-V

By Zdeněk Přikryl - 27 Jul, 2023 - Comments: 0

RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules from ratified/standard ISA extensions, such as integer instructions or floating-point instructions, designers can add custom instructions: pure design freedom! And the reasons for adding instructions are man... » read more

Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V

By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V" was published by researchers at TU Munich and Fraunhofer Institute for Applied and Integrated Security (AISEC). Abstract "Fault-injection attacks are a risk for any computing system executing security-relevant tasks, such as a secure boot process. While ha... » read more

Optimizing Hardware Capacity, Utilizing Automatic Differentiation to Efficiently Compute Derivatives in Parallel Programming Models

By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "Scalable Automatic Differentiation of Multiple Parallel Paradigms through Compiler Augmentation" was published by researchers at MIT (CSAIL), Argonne National Lab, and TU Munich. The paper was a Best Paper Finalist and a Best Student Paper winner at SuperComputing 2022. Find the technical paper here. Published November 2022. The work "demonstrates how Enzyme opti... » read more

Custom Compiler Technology Highlights from 2022.06 Release

By Synopsys - 27 Jul, 2022 - Comments: 0

Weikai Sun, VP of Engineering at Synopsys, highlights the key technologies in Custom Compiler’s latest release. He shows how Synopsys’ innovative solutions for design closure, layout automation and emerging applications are increasing the productivity of design teams. Click here to access the video white paper. » read more

Impact Of Instruction Memory On Processor PPA

By Roddy Urquhart - 24 Nov, 2020 - Comments: 0

The area of any part of a design contributes both to the silicon cost and to the power consumption. A simplistic following of the “A” in a processor IP vendor’s PPA numbers can be misleading. A processor is never in isolation but is part of a subsystem additionally including instruction memory, data memory, and peripherals. In most cases, instruction memory will be dominant and the proc... » read more

Fusion Compiler: Comprehensive RTL-to-GDSII Implementation System

By Synopsys - 07 Nov, 2018 - Comments: 0

The semiconductor industry is going through a renaissance period with waves of technological advancements and innovation. There has been a significant uptick in demand for silicon in recent years, driven by market sectors including automotive, artificial intelligence, cloud computing, and internet of things (IoT) that have their own unique mix of design and implementation requirements. The mobi... » read more

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Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Compiler

Re-Targetable LLVM C/C++ Compiler For RISC-V

Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V

Optimizing Hardware Capacity, Utilizing Automatic Differentiation to Efficiently Compute Derivatives in Parallel Programming Models

Custom Compiler Technology Highlights from 2022.06 Release

Impact Of Instruction Memory On Processor PPA

Fusion Compiler: Comprehensive RTL-to-GDSII Implementation System

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