Non-Stateful Logic Gates in ReRAM (RWTH Aachen, FZJ)


A new technical paper titled "Experimental Verification and Evaluation of Non-Stateful Logic Gates in Resistive RAM" was published by researchers at RWTH Aachen University and Forschungszentrum Jülich GmbH (FZJ). Abstract "Resistively switching, non-volatile memory devices facilitate new logic paradigms by combining storage and processing elements. Several non-stateful concepts such as Sco... » read more

Increasing AI Energy Efficiency With Compute In Memory


Skyrocketing AI compute workloads and fixed power budgets are forcing chip and system architects to take a much harder look at compute in memory (CIM), which until recently was considered little more than a science project. CIM solves two problems. First, it takes more energy to move data back and forth between memory and processor than to actually process it. And second, there is so much da... » read more

Optimizing Projected PCM for Analog Computing-In-Memory Inferencing (IBM)


A new technical paper titled "Optimization of Projected Phase Change Memory for Analog In-Memory Computing Inference" was published by researchers at IBM Research. "A systematic study of the electrical properties-including resistance values, memory window, resistance drift, read noise, and their impact on the accuracy of large neural networks of various types and with tens of millions of wei... » read more

Information flow policies for NVM Technologies


A new technical paper titled "Automated Information Flow Analysis for Integrated Computing-in-Memory Modules" was published by researchers at RWTH Aachen University. Abstract: "Novel non-volatile memory (NVM) technologies offer high-speed and high-density data storage. In addition, they overcome the von Neumann bottleneck by enabling computing-in-memory (CIM). Various computer architectures... » read more

Efficient Neuromorphic AI Chip: “NeuroRRAM”


New technical paper titled "A compute-in-memory chip based on resistive random-access memory" was published by a team of international researchers at Stanford, UCSD, University of Pittsburgh, University of Notre Dame and Tsinghua University. The paper's abstract states "by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present ... » read more