Pinpointing Timing Delays in Complex SoCs

Telemetry circuits are becoming a necessity in complex heterogeneous chips and packages to show how these devices are behaving post-production, but fusing together relevant data to identify the sources of problems adds its own set of challenges. In the past, engineering teams could build margin into chips to offset any type of variation. But at advanced nodes and in advanced packages, tolera... » read more

The Brave New World Of FinFETs

SoCs using 16nm and 14nm finFETs are expected to begin rolling out next year using a 20nm back-end-of-line process. While the initial performance and power numbers are looking very promising, the challenges of designing and building these complex chips are daunting—and there are more problems on the way. First, the good news. Initial results from foundries show a 150% improvement in perfor... » read more