tag: Coventor

What Happened To Inverse Lithography?
By Mark LaPedus - 20 Oct, 2016 - Comments: 2

Nearly 10 years ago, the industry rolled out a potentially disruptive technique called inverse lithography technology (ILT). But ILT was ahead of its time, causing the industry to push out the technology and relegate it to niche-oriented applications. Today, though, ILT is getting new attention as the semiconductor industry pushes toward 7nm, and perhaps beyond. ILT is not a next-generation ... » read more

FinFET Front-End-of-Line (FEOL) Process Integration With SEMulator3D
By Coventor - 19 Oct, 2016 - Comments: 0

Purely geometric scaling of transistors ended around the 90-nanometer (nm) era. Since then, most power/performance and area/cost improvements have come from structural and material innovations. Silicon-on-Insulator (SOI), first “partially depleted” and more recently “fully depleted” as well as embedded stressors, High-K / Metal-Gate (HKMG) and now FinFETs are examples of technology inno... » read more

Design Process Technology Co-Optimization For Manufacturability
By Dalong Zhao - 22 Sep, 2016 - Comments: 0

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology... » read more

Mask Maker Worries Grow
By Mark LaPedus - 22 Sep, 2016 - Comments: 0

Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts. For one thing, the features on the [getkc id="265" kc_name="photomask"] are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fab... » read more

Sorting Out Next-Gen Memory
By Mark LaPedus - 22 Sep, 2016 - Comments: 8

In the data center and related environments, high-end systems are struggling to keep pace with the growing demands in data processing. There are several bottlenecks in these systems, but one segment that continues to receive an inordinate amount of attention, if not part of the blame, is the memory and storage hierarchy. [getkc id="92" kc_name="SRAM"], the first tier of this hierarchy, is... » read more

Defect Evolution In Next-Generation Extreme Ultraviolet Lithography
By Coventor - 21 Sep, 2016 - Comments: 0

Extreme ultraviolet (EUV) lithography is a promising next generation lithography technology that may succeed optical lithography at future technology nodes. EUV mask infrastructure and manufacturing of defect-free EUV mask blanks is a key near term challenge in the use of EUV lithography. Virtual fabrication is a computerized technique to perform predictive, three dimensional modeling of sem... » read more

Faster Time To Yield
By Ed Sperling - 23 Aug, 2016 - Comments: 2

Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation. SE: Why does it take so long to get a chip all the way through to manufacturing? Jamiolkowski: There are three parts to that. There is a research side. You want to be able to explore new th... » read more

Making Phones Better
By Mattan Kamon - 18 Aug, 2016 - Comments: 0

Beneath a smartphone's slick packaging is some interesting, highly sophisticated technology that makes the user experience what it is today. Much of that experience relies on satisfying our ever growing desire for more data capacity for video, social media and the like. Providing that capacity relies on robust filtering to receive just your data stream amongst many nearby other streams. But tha... » read more

What Transistors Will Look Like At 5nm
By Mark LaPedus - 18 Aug, 2016 - Comments: 3

Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner. The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node. But 5nm technology presents a multitude of unknowns and challenges. For one thing, the exact timing and specs of 5nm remain cloudy. The... » read more

Back-End-of-Line (BEOL) Virtual Patterning With SEMulator3D
By Coventor - 17 Aug, 2016 - Comments: 0

Interconnect requirements for the 22nm technology node and beyond, driven by shrinking FEOL geometry, push the limits of unit process tools for BEOL as well as FEOL. Lengthy and costly in-fab experiments are required to ensure that the integrated BEOL process meets local performance and cross-wafer uniformity requirements. Virtual fabrication experiments conducted with SEMulator3D can reduce th... » read more

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