Partitioning In The Chiplet Era
Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.
What Comes After HBM For Chiplets
The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?
Memory Fundamentals For Engineers
eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.
Chip Industry Week In Review
Infineon’s 300mm power GaN wafer; SIA’s state of the industry report; India’s IC buzz; mandatory AI reporting; conference announcements; secure chips for space.
Defect Challenges Grow At The Wafer Edge
Better measurement of edge defects can enable higher yield while preventing catastrophic wafer breakage, but the number of possible defects is increasing.
Intel Vs. Samsung Vs. TSMC
Foundry competition heats up in three dimensions and with novel technologies as planar scaling benefits diminish.
Partitioning In The Chiplet Era
Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.
Controlling Warpage In Advanced Packages
Mechanical stresses increase with larger sizes and heterogeneous materials.
3.5D: The Great Compromise
Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.
Legacy Process Nodes Going Strong
The critical, and growing, significance of mature node chips and processes.
AI’s Role In Chip Design Widens, Drawing In New Startups
Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.
Key Technologies To Extend EUV To 14 Angstroms
Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.
Chip Industry Week In Review
Softbank's acquisition; advanced packaging funding; glass substrates; engineered copper wire; semi equipment set new record; HBM4; AI chips rake in funding; X-ray inspection; apprenticeships.
