tag: CTS

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs (Kyungpook National University)
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs” was published by researchers at Kyungpook National University. Abstract: "Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and sp... » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 02 Aug, 2019 - Comments: 0

Products/Services Rambus agreed to acquire Hillsboro, Ore.-based Northwest Logic, a purveyor of memory, PCIe, and MIPI digital controllers. The transaction is expected to close in the current quarter. Financial terms weren’t disclosed; Rambus said in a statement, “Although this transaction will not materially impact 2019 results due to the expected timing of close and acquisition accountin... » read more

The Trouble With Clock Trees
By Arvind Narayanan - 11 Oct, 2012 - Comments: 0

By Arvind Narayanan Among the perennial challenges of advanced-node IC design is power reduction. Clock trees are now the single largest source of dynamic power consumption, which makes clock tree synthesis (CTS) and optimization an important task for achieving overall power savings. Building a well-balanced clock tree and effectively managing clock skew has been a challenge since the first... » read more

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy