The Sub-2nm Paradox
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
Chip Industry Week In Review
Taiwan, Europe packaging buildout; 2nm ramps; quantum big $; 2 new university hubs; agent honeypots; Samsung strike averted; extreme environment chip design; quantum-dot qubit device fabricated w/high-NA EUV; EU flagship power electronics project; CNTs.
Chip Industry Week In Review
AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; memory test facility; Taiwan investments; SiC teamup; DRAM sizing; sequentially stacking silicon; MIPI A-PHY SerDes automotive compliance.
With Chiplets, What Role Does Economics Play?
Costs can rise with chiplets. Will that change? Will it matter?
Confusion Grows With More Interconnect Options And Tradeoffs
Each standard serves a specific use case, so chip architects are choosing more than one for a single design.
Can A Computer Science Student Be Taught To Design Hardware?
To fill the talent gap, CS majors could be taught to design hardware, and the EE curriculum could be adapted or even shortened.
Advanced Packaging Limits Come Into Focus
Mechanical and process control limits are now shaping what can be manufactured at scale.
Startup Funding: Q1 2026
Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.
All AI Data Center Interconnects Will Be Optical Within 5 Years
InP and SiPho join CMOS as critical technologies. Lasers, CPO and OCS will be everywhere (indium phosphide, silicon photonics, co-packaged optics, optical circuit switch).
Making Hybrid Bonding Better
Why this technology is so essential for multi-die assemblies, and how it can be improved.
When Semiconductor Materials Misbehave
The gap between lab performance and fab reality is growing wider as packages grow more complex.
Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers
Moving the power delivery network to the backside of a chip reduces congestion, but it introduces new challenges for fabs.
The Sub-2nm Paradox
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
