How The Electronics Industry Can Shape A More Sustainable, Energy-Efficient World


By Piyush Sancheti and Godwin Maben We’re already experiencing the effects of our world’s changing climate—devastating wildfires, prolonged droughts, torrential flooding, just to name a few examples. Global energy consumption is increasing, raising carbon dioxide levels and triggering extreme weather conditions. Two key forces driving these trends are the shift to hyperscale datacenter... » read more

Chip Sandwich: Electronics Chip & Photonics Chip Co-Optimized To Work Together (CalTech/Univ. of Southampton)


A technical paper titled "A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators" was published by researchers at CalTech and University of Southampton. "The resulting optimized interface between the two chips allows them to transmit 100 gigabits of data per second while producing just 2.4 pico-Joules per transmitted bit. This improves th... » read more

Effective Measurement Is The Key To Meeting Environmental Sustainability Goals In Data Centers


Hyperscale compute, using high-performance connected processors, continually transforms our lives as more and more applications rely on this type of compute, and at the heart of this hyperscale revolution are data centers. It is estimated that an equal amount of power is required for the airflow and cooling systems as for IT equipment. The pressure is on for organizations to create and adopt l... » read more

Securing Accelerator Blades For Datacenter AI/ML Workloads


Data centers handle huge amounts of AI/ML training and inference workloads for their individual customers. Such a vast number of workloads calls for efficient processing, and to handle these workloads we have seen many new solutions emerge in the market. One of these solutions is pluggable accelerator blades, often deployed in massively parallel arrays, that implement the latest state-of-the-ar... » read more

HBM3 In The Data Center


Frank Ferro, senior director of product management at Rambus, talks about the forthcoming HBM3 standard, why this is so essential for AI chips and where the bottlenecks are today, what kinds of challenges are involved in working with this memory, and what impact chiplets and near-memory compute will have on HBM and bandwidth.     » read more

Why Silent Data Errors Are So Hard To Find


Cloud service providers have traced the source of silent data errors to defects in CPUs — as many as 1,000 parts per million — which produce faulty results only occasionally and under certain micro-architectural conditions. That makes them extremely hard to find. Silent data errors (SDEs) are random defects produced in manufacturing, not a design bug or software error. Those defects gene... » read more

CXL 3.0: From Expansion To Scaling


At the Flash Memory Summit in August, the CXL Consortium released the latest, and highly anticipated, version 3.0 of the Compute Express Link (CXL) specification. This new version of the specification builds on previous generations and introduces several compelling new features that promise to increase data center performance and scalability, while reducing the total cost of ownership (TCO). ... » read more

IC Architectures Shift As OEMs Narrow Their Focus


Diminishing returns from process scaling, coupled with pervasive connectedness and an exponential increase in data, are driving broad changes in how chips are designed, what they're expected to do, and how quickly they're supposed to do it. In the past, tradeoffs between performance, power, and cost were defined mostly by large OEMs within the confines of an industry-wide scaling roadmap. Ch... » read more

The Drive Toward More Predictive Maintenance


Maintenance is a critical behind-the-scenes activity that keeps manufacturing facilities running and data centers humming. But when not performed in a timely manner, it can result in damaged products or equipment, or significant system/equipment downtime. By shifting from scheduled maintenance to predictive maintenance, factories and electronic system owners can reap substantial benefits, in... » read more

Finding the Scope of CXL-Enabled Tiered Memory System in Production


This new technical paper titled "TPP: Transparent Page Placement for CXL-Enabled Tiered Memory" is presented by researchers at University of Michigan and Meta Inc. Abstract (partial) "We propose a novel OS-level application-transparent page placement mechanism (TPP) for efficient memory management. TPP employs a lightweight mechanism to identify and place hot and cold pages to appropriate... » read more

← Older posts Newer posts →