tag: debug

The Rise Of Complex Debug On Heterogeneous Multicore SoCs
By Kathy Tufto - 25 Aug, 2016 - Comments: 0

When projects move away from discrete development of loosely coupled systems to an integrated heterogeneous environment, elephantine debugging challenges are created. These challenges do not exist during discrete development because developers are able to design, develop, test, and optimize within the confines of their own device. But when consolidating heterogeneous systems, developers and ... » read more

FPGA Prototyping Gains Ground
By Jeff Dorsch - 25 Aug, 2016 - Comments: 0

FPGA technology for design prototypes is making new inroads as demands increase for better integration between hardware and software. [gettech id="31071" comment="FPGA"] prototyping, also known as physical prototyping, has been supported by all of the major EDA players for some time, and it has been considered an essential tool for the largest chipmakers, along with emulation and simulation.... » read more

Managing Quality With Developer Desktop Analysis
By Synopsys - 24 Aug, 2016 - Comments: 0

Even the most seasoned developer is prone to introducing a few new bugs in new or modified code. Static analysis is a great solution to help development teams find and fix those issues. Now with Coverity’s new desktop analysis capabilities, developers can find and fix their own defects before checking their code into the source control management system – and before anyone else finds the de... » read more

Optimizing Emulator Utilization
By Russell Klein - 11 Aug, 2016 - Comments: 0

The growing pressures of market schedules, design complexity and the ever-increasing amount of embedded software in today’s SoCs has put verification in the hot-seat. Now that new emulation tools can link hardware and software verification, SoC designers are turning to emulation more than ever before to debug embedded software. The standard method for debugging software with an emulator is wi... » read more

Colorless vs. Colored Double-Patterning Design Flows
By David Abercrombie - 21 Jul, 2016 - Comments: 0

Colored vs. Colorless double patterning design flows—do you know which one is best for your design? What options does your foundry allow? Do you debug one differently from the other? In this short video, I’ll demonstrate the differences between colored and colorless DP design flows, and explain the options and potential pitfalls of each approach. With a better understanding of how to design... » read more

Sharing Information About Corner Cases
By Ed Sperling - 07 Jul, 2016 - Comments: 0

The definition of what is good enough when it comes to new technology is still evolving. In safety-critical applications, as well as a number of other areas such as drones or domestic robots, people will need to watch over all machines very closely rather than the other way around. While these machines may serve a useful purpose, they also need to be monitored to ensure they don't go too far as... » read more

Executive Insight: Raik Brinkmann
By Ed Sperling - 06 Jul, 2016 - Comments: 0

[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down with Semiconductor Engineering to discuss where and why formal verification is gaining traction, and how it fits alongside other verification approaches. What follows are excerpts of that conversation. SE: [getkc id="33" kc_name="Formal"] has been around for a whi... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 15 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, vice president of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_nam... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 09 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, VP of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_name="Mentor Gr... » read more

Open Standards For Verification?
By Ann Mutschler - 01 Jun, 2016 - Comments: 0

The increasing use of verification data for analyzing and testing complex designs is raising the stakes for more standardized or interoperable database formats. While interoperability between databases in chip design is not a new idea, it has a renewed sense of urgency. It takes more time and money to verify increasingly complex chips, and more of that data needs to be used earlier in the fl... » read more

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