Who’s Profiting From Complexity

By Ed Sperling - 21 Dec, 2015 - Comments: 0

Tool vendors' profits increasingly are coming from segments that performed relatively poorly in the past, reflecting both a rise in complexity in designing chips and big improvements in the tools themselves. The impacts of power, memory congestion, advanced-node effects such as process variation, [getkc id="160" kc_name="electromigration"] and RC delay in [getkc id="36" kc_name="interconnect... » read more

When Order Matters

By Mentor, a Siemens Business - 17 Dec, 2015 - Comments: 0

Debugging DP errors can be not only time-consuming, but also frustrating, when new errors seem to appear out of nowhere. The order in which you address DP errors can make a significant difference in the efficiency of your debug efforts. Learning the sequence of ordered DP debugging explained in this white paper can not only help you reduce the time you spend analyzing and fixing DP errors, but ... » read more

You’re Not Alone

By Srinivas Velivala - 19 Nov, 2015 - Comments: 0

All too often we get caught up in our own work and our own issues, thinking no one else could possibly be having as much trouble as we are. The reality is that many, if not most, of the problems and challenges in IC verification are not unique to one design, one team, or one person. The natural reluctance of people to admit they are struggling with some aspect of their job often keeps them from... » read more

UltraSoC: Debug IP

By Ed Sperling - 03 Nov, 2015 - Comments: 0

The background noise across the engineering community is rising with the growing complexity of SoCs. While the big news several years ago was the introduction of chips with 1 billion transistors, that's no longer making headlines. There are now well over 1 billion transistors in advanced SoCs and more than 100 IP blocks. Even abstractions are beginning to break down (see related story). Ent... » read more

You Can’t Walk Straight Blindfolded

By Tom De Schutter - 29 Oct, 2015 - Comments: 0

Let’s examine the first part of the title of this blog. It is stated as a given. But is it true that you really can’t walk straight when blindfolded? That is what my children and I set out to investigate one sunny afternoon in October (yes we live in California). We looked for a nice open field with little to no surrounding sound, so that you cannot use the sound to set your bearing. We ... » read more

Double Patterning Custom Design And Debug

By Mentor, a Siemens Business - 22 Oct, 2015 - Comments: 0

Litho-Etch-Litho-Etch (LELE) double pattern (DP) processing affects many aspects of the design flow at/below the 20 nm node level. This can be very disruptive for the custom designer, impacting basic cell design strategy, layout rules and debug as well as parasitic extraction. This paper discusses how to deal with these impacts, avoid common design mistakes, and debug quickly and accurately. ... » read more

Tech Talk: SoC Protocol Debug

By Ed Sperling - 24 Sep, 2015 - Comments: 0

Bernie DeLay, group director for verification IP R&D at Synopsys, talks about what goes wrong in complex SoCs, how so-called standard pieces play together, and where are the gotchas in re-use. [youtube vid=AaY_AmdjUpo] » read more

A Word About FPGA-Based Prototyping

By Tom De Schutter - 24 Sep, 2015 - Comments: 0

With software now driving the main capabilities of embedded devices, prototyping has taken the spotlight in SoC design. This is turning a once-hardware-centric electronics supply chain upside down. To cope with this new reality, companies are embracing both virtual and physical prototyping technologies. Physical prototyping, also known as FPGA-based prototyping, is an important piece of an e... » read more

SoC Verification Made Easy With Aldec HES-DVM

By Aldec - 23 Sep, 2015 - Comments: 0

As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, therefore one option is to use an FPGA emulator to speed up the design process. But what happens when a bug occurs? This document... » read more

Making Hardware Design More Agile

By Ed Sperling - 12 Aug, 2015 - Comments: 1

Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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