tag: debug

Getting Formal About Debug
By Brian Bailey - 25 Feb, 2016 - Comments: 0

While much of the design and verification flows have been automated, debug remains the problem child. It has defied automation and presents a management nightmare due to the variability of the process. In recent articles about debug, we examined how much time development teams spend in the debug process and some of the reasons why it is becoming a bigger problem. This includes issues such as ex... » read more

UVM: It’s Organized And Systematic
By Henry Chan - 25 Feb, 2016 - Comments: 0

One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain. You always want a good foundation and development of strong fundamentals in any endeavor. Verification is no different and UVM hammers the fundamental... » read more

Debug: Last Bastion Of Automation
By Brian Bailey - 27 Jan, 2016 - Comments: 0

There have been a number of times when anecdotal evidence became folk law and then over time, the effort was put in to find out whether there was any truth in it. Perhaps the most famous case is the statement that verification consumes 70% of development time and resources. For years this “fact” was used in almost every verification presentation and yet nobody knew where the number had come... » read more

Who’s Profiting From Complexity
By Ed Sperling - 21 Dec, 2015 - Comments: 0

Tool vendors' profits increasingly are coming from segments that performed relatively poorly in the past, reflecting both a rise in complexity in designing chips and big improvements in the tools themselves. The impacts of power, memory congestion, advanced-node effects such as process variation, [getkc id="160" kc_name="electromigration"] and RC delay in [getkc id="36" kc_name="interconnect... » read more

When Order Matters
By Mentor, a Siemens Business - 17 Dec, 2015 - Comments: 0

Debugging DP errors can be not only time-consuming, but also frustrating, when new errors seem to appear out of nowhere. The order in which you address DP errors can make a significant difference in the efficiency of your debug efforts. Learning the sequence of ordered DP debugging explained in this white paper can not only help you reduce the time you spend analyzing and fixing DP errors, but ... » read more

You’re Not Alone
By Srinivas Velivala - 19 Nov, 2015 - Comments: 0

All too often we get caught up in our own work and our own issues, thinking no one else could possibly be having as much trouble as we are. The reality is that many, if not most, of the problems and challenges in IC verification are not unique to one design, one team, or one person. The natural reluctance of people to admit they are struggling with some aspect of their job often keeps them from... » read more

UltraSoC: Debug IP
By Ed Sperling - 03 Nov, 2015 - Comments: 0

The background noise across the engineering community is rising with the growing complexity of SoCs. While the big news several years ago was the introduction of chips with 1 billion transistors, that's no longer making headlines. There are now well over 1 billion transistors in advanced SoCs and more than 100 IP blocks. Even abstractions are beginning to break down (see related story). Ent... » read more

You Can’t Walk Straight Blindfolded
By Tom De Schutter - 29 Oct, 2015 - Comments: 0

Let’s examine the first part of the title of this blog. It is stated as a given. But is it true that you really can’t walk straight when blindfolded? That is what my children and I set out to investigate one sunny afternoon in October (yes we live in California). We looked for a nice open field with little to no surrounding sound, so that you cannot use the sound to set your bearing. We ... » read more

Double Patterning Custom Design And Debug
By Mentor, a Siemens Business - 22 Oct, 2015 - Comments: 0

Litho-Etch-Litho-Etch (LELE) double pattern (DP) processing affects many aspects of the design flow at/below the 20 nm node level. This can be very disruptive for the custom designer, impacting basic cell design strategy, layout rules and debug as well as parasitic extraction. This paper discusses how to deal with these impacts, avoid common design mistakes, and debug quickly and accurately. ... » read more

Tech Talk: SoC Protocol Debug
By Ed Sperling - 24 Sep, 2015 - Comments: 0

Bernie DeLay, group director for verification IP R&D at Synopsys, talks about what goes wrong in complex SoCs, how so-called standard pieces play together, and where are the gotchas in re-use. [youtube vid=AaY_AmdjUpo] » read more

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