More Than Moore

By Ed Sperling - 21 Aug, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at Open-Silicon; Patrick Soheili, vice president and general manager of IP Solutions at eSilicon; Brandon Wang, engineering group director at Cadence; John Ferguson, product manager for DRC applications at Mentor Graphics; and Kevin Kranen, d... » read more

SoC Derivatives Made Easy

By Various Writers - 14 Feb, 2013 - Comments: 0

Today’s system-on-a-chip (SoC) designs are creating more challenges than ever – challenges that demand bringing the product to market faster, before the competition does. The electronics industry and growing competition require that SoC’s achieve a short time to market (TTM) while design complexity continues to grow at a rapid rate. Another challenge is to keep the SoC design and overall ... » read more

Investment Options

By Ed Sperling - 31 Jul, 2012 - Comments: 0

It's clear that something fundamental has changed in the semiconductor manufacturing industry. What's less clear is how this will play out over the long term. Intel's agreement to invest more than $4 billion in ASML to ensure the continued development of EUV and 450mm wafer technology is more than just a one-off deal. It's a very public recognition that the astronomical cost of design and ma... » read more

SoC Design In 5 Years

By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ed Sperling The semiconductor industry is used to looking at changes every couple of years, based upon the progression of Moore’s Law. But look out further, over the next five years when the most advanced process node is somewhere between 14nm and 16nm, and the job of designing and manufacturing an SoC will look very different. At the center of this change are three very significant tr... » read more

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Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: derivatives

More Than Moore

SoC Derivatives Made Easy

Investment Options

SoC Design In 5 Years

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