Better Choreography Required For Complex Chips

The rapidly growing number of features and options in chip design are forcing engineering teams to ratchet up their planning around who does what, when it gets done, and how various components will interact. In effect, more elements in the design flow need to be choreographed much more precisely. Some steps have to shift further left, while others need to be considered earlier in the plannin... » read more

Beyond The Water Cooler: 2020 Report On IC/ASIC Design And Verification Trends

Verification and design engineers like to talk shop and discuss their experiences and visions. But even though engineers sharing stories around the water cooler (whatever form that takes—conferences, blogs, etc.) does provide all kinds of valuable insights, it doesn’t provide the full picture into the very large and complicated and extremely dynamic global semiconductor industry. To better ... » read more

Balancing Implementation Time, Complexity, Schedule

Design complexity today is demanding all the creativity a design engineer can muster to figure out the best ways to optimize a design for the power situation the device will be operating under. Advanced techniques are being leveraged, to be sure, but in varying degrees, perhaps in part because these techniques impact the complexity of the design implementation. If there are four or five ... » read more

High-Level Gaps Emerge

Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow, and why it is needed at present with Leah Clark, associate technical director for digital video technology at [getentity id="22649" e_name="Broadcom"]; Jon McDonald, technical marketing engineer at [getentity id="22017" e_name="Mentor Graphics"]; Phil Bishop, vice president of the System Level D... » read more