Increased design size is only one dimension of the growing complexity challenge.
Verification and design engineers like to talk shop and discuss their experiences and visions. But even though engineers sharing stories around the water cooler (whatever form that takes—conferences, blogs, etc.) does provide all kinds of valuable insights, it doesn’t provide the full picture into the very large and complicated and extremely dynamic global semiconductor industry. To better inform those chats, both casual and formal, the Wilson Research Group conducts a bi-annual survey of important trends in FPGA and ASIC functional verification and summarize our findings and analysis here in a four-part series, of which this is the third article.
In the previous two articles, Verification Effectiveness in the Face of FPGA Complexity and Trends in FPGA Verification Effort and Technology Adoption, we discussed FPGA design and verification trends. We now shift our focus to IC/ASIC trends and present our overall conclusions. In this article we look at design and design resources that reflect growing design complexity as well as trends in verification technology adoption.
Figure 1 shows trends from the 2012 through 2020 studies in terms of active IC/ASIC design project by design sizes (gates of logic and data path, excluding memories). Keep in mind that the graph represents the percentage of study participants, not silicon volume.
One interesting observation from this year’s study is the continuing increase in design participants working on designs of less than 100M gates. This is due to a number of participants working on smaller sensor chips for IoT and automotive devices. As we’ll see, this yielded some interesting study results.
Fig. 1: IC/ASIC study participation by gate count (design size).
A key takeaway from figure 1 is that the electronic industry continues to move to larger designs. In fact, 36% of today’s design projects are working on designs over 80M gates, while 31% of today’s design projects are working on designs between 1M gates and 80M gates.
But increased design size is only one dimension of the growing complexity challenge. One industry driver that has had a substantial impact on IC/ASIC design and verification complexity is the emergence of new layers of design requirements (beyond basic functionality), which did not exist years ago; for example, security requirements, safety requirements, and requirements associated with hardware-software interactions in embedded processor designs. What has changed significantly in designs since the original Collett studies is the dramatic move to SoCs. In 2004, Collett found that 52% of designs contained one or more embedded processors.
Our 2020 study found that 68% of design projects were working on designs with embedded processors, as shown in figure 2. In 2016 we found that 73% of projects were working on the designs with embedded processors. This drop is due to the significant increase in the number of projects involving smaller designs. This large increase in smaller designs has an overall impact on the number of designs containing embedded processors. If we ignore these smaller designs and only look at designs greater than 1M gates, we did not see a statistically significant change in the number embedded processors from 2016 to 2020.
Fig. 2: Number of embedded processors in an IC/ASIC design.
Another interesting trend is the increase in the number of multiple embedded processes in a single SoC. For example, 48% of design projects today are working on designs that contain two or more embedded processors, while 17% of today’s designs include eight or more embedded processors. SoC class designs add a new layer of verification complexity to the verification process that did not exist with traditional non-SoC class designs due to hardware and software interactions, new coherency architectures, and the emergence of complex network on-a-chip interconnect.
Our 2020 study, for the first time, tracked the number of IC/ASIC projects that have incorporated a RISC-V processor in their design, which was 23%, as shown in figure 3. In addition, we tracked the number of IC/ASIC projects that have incorporated some type of AI accelerator processor (e.g., TPU, etc.), which was 27%.
Fig. 3: Percentage of new IC/ASIC designs incorporating AI and RISC-V processors.
Many projects implement security features in their designs, as shown in figure 4. These security features add requirements and complexity to the verification process.
Fig. 4: IC/ASIC design projects implementing security features.
Safety-critical designs also see an increase in requirements contributing to complexity. Figure 5 reveals an increase in the number of IC/ASIC projects working under one of multiple safety-critical development process standards or guidelines.
Fig. 5: IC/ASIC safety-critical design projects.
For those projects working under a safety-critical development process standard or guideline, in figure 6 we show the specific breakdown for the various standards. Note that some projects are required to work under multiple safety standards or guidelines; for example, IEC61508 and IEC61511.
Fig. 6: Safety-critical development standard used on IC/ASIC project.
Clearly, IC/ASIC designs are clearly growing in complexity, which impacts verification effort and effectiveness. Now we will discuss the growing IC/ASIC design project resource trends due to this rising design complexity.
Figure 7 shows the percentage of total IC/ASIC project time spent in verification. You can see two extremes in this graph. In general, projects that spend very little time in verification are typically working on designs with a good deal of existing pre-verified design IP, which is integrated to create a new product. On the other extreme, projects that spend a significant amount of time in verification often have a high percentage of newly developed design IP that must be verified. Note the increase in project times greater than 60% for this year’s study. Again, this is a potential indication of growing design and verification complexity.
Fig. 7: Percentage of IC/ASIC project time spent in verification.
Perhaps one of the biggest challenges today is to control cost and engineering headcount, which means identifying IC/ASIC design and verification solutions that increase productivity. To illustrate the need for productivity improvement, we discuss the trend in terms of increasing engineering headcount. Figure 8 shows the mean peak number of IC/ASIC engineers working on a project.
Fig. 8: Mean number of peak engineers per IC/ASIC project.
While, on average, the demand for IC/ASIC design engineers grew at about a 3% CAGR between 2007 and 2020, the demand for IC/ASIC verification engineers grew at a 6.8% CAGR. Today, on average, across all market segments, we find about a one-to-one ratio in terms of mean peak number of verification and design engineers. However, in some market segments, such as processors, it is not unusual to find a 5-to-1 ratio.
But verification engineers are not the only project stakeholders involved in the verification process. Design engineers spend a significant amount of their time in verification too, as shown in figure 9. However, the data indicate a trend toward IC/ASIC design engineers spending slightly less time involved in verification tasks, when compared to 2014.
Fig. 9: Where IC/ASIC design engineers spend their time.
Figure 10 shows where verification engineers spend their time (on average). Our study found that IC/ASIC verification engineers spend more of their time debugging than with any other activity. From a management perspective, this can be a significant challenge when planning future projects’ effort and schedule based on previous projects’ data since debugging is unpredictable and varies significantly between projects.
Fig. 10: Where IC/ASIC verification engineers spend their time.
As we’ve observed, the IC/ASIC market in the mid-2000 timeframe underwent growing pains to address increased verification complexity, predominately brought on with the adoption of SoC-class designs. This maturing of IC/ASIC projects’ processes is clearly visible when comparing various simulation-based verification technology adoption trends from 2007 through 2020 as shown in figure 11.
Fig. 11: IC/ASIC verification technology adoption trends (2007-2020).
Figure 12 shows the IC/ASIC adoption trends for formal property checking (e.g., model checking), as well as automatic formal applications. Examples of automatic formal application tools include: SoC integration connectivity checking, deadlock detection, X semantic safety checks, coverage reachability analysis, and many other properties that can be automatically extracted and then formally proven. The graph shows that formal property checking has grown at a 6.7% CAGR since 2012, while automatic formal applications have grown at a 12.8% CAGR.
Fig. 12: IC/ASIC formal technology adoption.
ESDA categorizes emulation and FPGA under “Other Logic Verification,” separate from logic simulation. They estimated the market value of this category at $650.6M in 2019. Various analysts expect this category to grow in the order of 8-10% CAGR by 2024.
Historically, the simulation market has depended on processor frequency scaling as one means of continual improvement in simulation performance. However, as processor frequency scaling leveled off in the mid-2000 timeframe, simulation-based techniques were unable to keep up with today’s growing complexity. This is particularly true when simulating large designs that include both software and embedded processor core models. Hence, acceleration techniques are now required to extend SoC verification performance for very large designs. In fact, emulation and FPGA prototyping have become key platforms for SoC integration verification where both hardware and software are integrated into a system for the first time. In addition to SoC verification, emulation and FPGA prototyping are also used today as a platform for software development.
Taking a deeper dive into the data we collected from this year’s study, we decided to partition the data for emulation and FPGA prototyping adoption by design size as follows: less than 1M gates, 1M to 80M gates, and greater than 80M gates, as shown in Figure 13. Notice that the project adoption of emulation continues to increase as design sizes increase. However, the adoption of FPGA prototyping does not follow a similar trend as design sizes increase beyond 80M gates.
Fig. 13: Emulation and FPGA prototyping adoption by ASIC/IC design size.
Hopefully this article has given you a wider perspective to help you make critical decisions about where to invest your money, time, and energy on verification technology and tools. Afterall, you can learn only so much around the water cooler. In the final installment of this series, we will discuss IC/ASIC trends in language and library adoption, power management, and verification results, and we will take a deeper dive into two somewhat surprising phenomena revealed in the data: the relationship between verification maturity and non-trivial bug escapes into production and the effect of safety critical design practices on the level of silicon success. Finally, we will conclude with a summary of the study and key findings.
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