Context-Aware Analysis Can Automatically Protect Critical Nets And Devices During Fill Insertion


Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly become a critical and essential technology that addresses the increasing complexity of geometrical checks used in both established and emerging integrated circuit (IC) technologies. Traditional electronic design automation (EDA) verification tools handle either the physical verifica... » read more

Re-Architecting SerDes


Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

Interface DRC Can Streamline Chip-Level Interface Physical Verification


In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning stages, blocks placed in the chip-level floorplan are usually still under development. Merging these incomplete blocks with the... » read more