Context-Aware Analysis Can Automatically Protect Critical Nets And Devices During Fill Insertion

By Dina Medhat - 27 Jul, 2023 - Comments: 0

Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly become a critical and essential technology that addresses the increasing complexity of geometrical checks used in both established and emerging integrated circuit (IC) technologies. Traditional electronic design automation (EDA) verification tools handle either the physical verifica... » read more

Re-Architecting SerDes

By Brian Bailey - 10 Dec, 2020 - Comments: 0

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

Interface DRC Can Streamline Chip-Level Interface Physical Verification

By James Paris - 26 Apr, 2018 - Comments: 0

In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning stages, blocks placed in the chip-level floorplan are usually still under development. Merging these incomplete blocks with the... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: design rule checks

Context-Aware Analysis Can Automatically Protect Critical Nets And Devices During Fill Insertion

Re-Architecting SerDes

Interface DRC Can Streamline Chip-Level Interface Physical Verification