tag: design under test

White-Box Fuzzer With Static Analysis To Detect And Locate Timing Vulnerabilities In RISC-V Processors 
By Technical Paper Link - 20 Feb, 2024 - Comments: 0

A technical paper titled “WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors” was published by researchers at Indian Institute of Technology Madras, Texas A&M University, and Technische Universität Darmstadt. Abstract: "Timing vulnerabilities in processors have emerged as a potent threat. As processors are the foundation of any computing s... » read more

LLMs For Hardware Design Verification
By Technical Paper Link - 16 Oct, 2023 - Comments: 0

A technical paper titled “LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation” was published by researchers at University of Cambridge, lowRISC, and Imperial College London. Abstract: "Test stimuli generation has been a crucial but labor-intensive task in hardware design verification. In this paper, we revolutionize this process by harnessing the power of large langua... » read more

Emulation’s Footprint Grows
By Brian Bailey - 27 Oct, 2016 - Comments: 0

It wasn't that many years ago that [getkc id="30" comment="emulation"] was an expensive tool available to only a few, but it has since become indispensable for a growing number of companies. One obvious reason is the growing size of designs and the inability of [getkc id="11" kc_name="simulation"] to keep up. But emulation also has been going through a number of transformations that have made i... » read more

U.V.M. Spells Relief
By Henry Chan - 22 Dec, 2015 - Comments: 0

Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly. So what is UVM? UVM is a verification meth... » read more

The Old Two-Step Just Doesn’t Have That Swing
By Lauro Rizzatti - 16 Jun, 2015 - Comments: 0

Power analysis has quickly become equally as important as functional verification for today's power-hungry SoCs. Yet, until now, it was not possible to fully analyze dynamic power in very large SoCs running embedded software. That day has finally arrived with new emulation platform software that overcomes the intrinsic shortcomings of the current two-step power estimation tools. The current ... » read more

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