Making DFM Work Better

By Ann Mutschler - 17 Dec, 2009 - Comments: 0

By Ann Steffora Mutschler At 65nm, design for manufacturing optimization and analysis has mostly been an afterthought. At 40nm and beyond, DFM has been pushed well up into the design phase. There are good reasons for this shift. What emerged at the 65nm node were signoff tools that understand manufacturing used in semiconductor design, said Manoj Chako, a product director for digital si... » read more

End User Report: Things To Do With Multicore

By Ed Sperling - 24 Sep, 2009 - Comments: 0

System-Level Design sat down with Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia, to talk about changes in the communications sector and how that’s affecting design. What follows are excerpts of that conversation. By Ed Sperling SLD: Where does multicore fit into the Freescale world? Lisa Su: The difference between us and an AMD and Intel ... » read more

Restrictive Design Rules, Take Two

By Ed Sperling - 27 Aug, 2009 - Comments: 0

By Ed Sperling For the past couple of years, restrictive design rules have been looming over advanced process nodes as the best way to get a chip out the door with minimal re-spins, on schedule and for the least amount of money. Even with immersion technology, 193nm wavelengths mean the laser beam is entirely too large to create the masks used to create complex systems on chip at 32nm and bel... » read more

Making Quality A Top Priority in Next-Generation Designs

By Cheryl Ajluni - 25 Jun, 2009 - Comments: 0

By Cheryl Ajluni With system design such a complicated task these days, it is increasingly likely that designers will inadvertently overlook some details of the design process, or worse yet, simply not have the time to address them adequately. Time is readily spent focusing on things like performance, area, timing, and power, but what about something a bit more esoteric in nature—namely, qu... » read more

EUV Is Late—And It Hurts

By Ed Sperling - 28 May, 2009 - Comments: 0

Most chip architects and engineers couldn’t give a whit about the difference between deep ultraviolet and extreme ultraviolet lithography. It’s traditionally been a problem that foundries had to wrestle with, and that was their problem. Even DFM has been slow to catch on because what’s done in a foundry is of little interest up front. The separation of those two worlds worked fine ... » read more

What Works…And What Doesn’t

By Ed Sperling - 02 Apr, 2009 - Comments: 0

Lisa Su, chief technology officer at Freescale, talks about the future of system-level design, what's working and where the problems are. [youtube vid=zw5dUTuO7DY] » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

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by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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