LVS Boxing Helps Designers Knock Out Designs Quickly

By Mentor, a Siemens Business - 18 Feb, 2016 - Comments: 0

Keeping up with the constant demand for better, faster design flow performance while preserving the original layout hierarchy of a design can be very challenging during design verification. Designers must constantly manage tradeoffs between performance, database size, and accuracy. In the early design cycle, using the LVS boxing capabilities of Calibre nmLVS to replace incomplete or missing blo... » read more

Tech Talk: Double-Triple Patterning

By Brian Bailey - 21 Jan, 2016 - Comments: 0

Mentor Graphics' David Abercrombie shows the differences and challenges in double patterning versus triple patterning. [youtube vid= e0wZmjBbEf0] » read more

Inside Multi-Beam E-Beam Lithography

By Mark LaPedus - 19 Nov, 2015 - Comments: 4

Semiconductor Engineering sat down with David Lam, chairman of Multibeam, a developer of multi-beam e-beam tools for direct-write lithography applications. Lam is also a venture capitalist. He founded Lam Research in 1980, but left as an employee in 1985. What follows are excerpts of that conversation. SE: How has the equipment business changed over the years and what’s the state of the i... » read more

Déjà Vu For CMP Modeling?

By Jeff Wilson - 17 Sep, 2015 - Comments: 0

One definition of design for manufacturing (DFM) is providing knowledge about the impact of the manufacturing process on a design layout to the designers, so they can use that information to improve the robustness, reliability, or yield of their design before tapeout. Essentially, DFM is about designers taking ownership of the full “lifecycle” of a design, and going beyond the required desi... » read more

MEMS Capacitance Extraction With Calibre xACT-3D Software

By Mentor, a Siemens Business - 20 Aug, 2015 - Comments: 0

The growing use of MEMS in today's complex products requires new approaches to capacitance calculation to ensure companies can meet their time-to-market targets while producing products that meet performance and reliability expectations. Freescale Semiconductor and Mentor Graphics collaborated to demonstrate that Calibre xACT-3D software provides a robust method for extracting node-to-node capa... » read more

Case Studies in P&R Double-Patterning Debug

By David Abercrombie - 20 Aug, 2015 - Comments: 0

In my last article, we looked at some case studies of the unique types of issues related to double patterning (DP) that place and route (P&R) and chip finishing engineers have to deal with. I’ve got some more interesting case studies to show you this time. In modern P&R designs, the metal routes on a particular layer are unidirectional (or at least primarily unidirectional). Long p... » read more

Ensuring Optimal Performance For Physical Verification

By Mentor, a Siemens Business - 22 Jul, 2015 - Comments: 0

By accessing the most recently qualified version of foundry rule files, users get the most efficient rule implementations. By adopting the most recent version of Calibre, users get the latest improvements in available operations, operation performance, data hierarchy optimization and total scaling, providing the best possible performance and minimizing runtimes. Design teams running full-chip D... » read more

Automated Chip Polishing Can Make Your Design Shine

By Bill Graupp - 21 May, 2015 - Comments: 1

Today’s modern chip design is a collaboration among many design teams, often using different design flows and different EDA tools. This state of the chip design industry can create high risk in the layout process, forcing delays in product release. To help reduce this risk, many levels of verification throughout the design flow exist to identify problematic areas in a design. While new EDA to... » read more

Faster Time To Root Cause With Diagnosis-Driven Yield Analysis

By Mentor, a Siemens Business - 16 Apr, 2015 - Comments: 0

ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed... » read more

3D Effects At 20nm And Beyond

By Ann Mutschler - 19 Mar, 2015 - Comments: 0

At the 20nm process node and below, attenuated phase shift masks (PSM) are used in the photolithography process, which results in approximately 70nm of topography. This now must be accounted for using 3D mask approximation. Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], explained that in terms of [getkc id="80" comment="lithography"], where simulation-based technologies are used,... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: DFM