tag: die-to-die interfaces

Holistic Die-to-Die Interface Design Methodology For 2.5-D Multi-Chip-Module Systems
By Fraunhofer IIS/EAS - 07 Dec, 2022 - Comments: 0

More than Moore technologies can be supported by system level diversification enabled by chiplet based integrated systems within multi-chip-modules (MCM) and silicon interposer based 2.5D systems. The division of large system-on-chip dies into smaller chiplets with different technology nodes specific to the chiplet application requirement enables the performance enhancement at system level whil... » read more

GUC GLink Test Chip Uses In-Chip Monitoring And Deep Data Analytics For High Bandwidth Die-To-Die Characterization
By proteanTecs - 11 Oct, 2022 - Comments: 0

Advanced ASIC leader Global Unichip Corp (GUC) has developed GLink, a high-bandwidth, low-latency, and power-efficient die-to-die (D2D) interface. GLink offers the industry’s highest optimized interconnect solution for both CoWoS and InFO packaging technologies. The GUC and proteanTecs collaboration started with GUC’s second generation of GLink, known as GLink 2.0. The project target was... » read more

From SerDes Chiplets To Die-To-Die Interfaces
By Mohit Gupta - 08 Jun, 2017 - Comments: 0

The demand for ever faster high-speed interfaces has never been quite so pronounced. In our increasingly connected world, petabytes of data are continuously generated by a wide range of devices, systems and IoT endpoints such as vehicles, wearables, smartphones and even appliances. The resulting digital tsunami has prompted industry heavyweights like Google, Microsoft, Facebook and Amazon to co... » read more

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