Integrating Digital Twins In Semiconductor Operations

By Mark da Silva - 22 Feb, 2024 - Comments: 0

By Mark da Silva, Nishita Rao and Karim Somani Chipmakers must adopt transformative technologies including Digital Twins (DT) to keep pace with unprecedented global semiconductor industry growth that is expected to drive its total market value to $1 trillion[1] as soon as 2030. Leveraging predictive modeling and other efficiency-enhancing innovations, DTs promise to optimize semiconductor d... » read more

Expecting The Unexpected: Analyzing A Data Center Cooling Failure

By Mark Seymour - 15 Feb, 2024 - Comments: 0

Data center thermal management is often a reactive process. Servers issue warning messages, monitoring alarms activate, or employees express concern about general temperature levels/hotspots and then management decides what to do next. For incremental issues, once known, the necessary steps can be taken to resolve or improve these issues; however, what happens when a potential thermal issue onl... » read more

Center For Deep Learning In Electronics Manufacturing: Bringing Deep Learning To Production For Photomask Manufacturing

By Jan Willis - 16 Nov, 2023 - Comments: 0

The Center for Deep Learning in Electronics Manufacturing (CDLe) was formed as an alliance between D2S, Mycronic and NuFlare Technology in autumn 2018. Assignees from each alliance partner worked with deep learning (DL) experts under the leadership of Ajay Baranwal, director of CDLe. The CDLe’s mission was to 1) turn DL into a core competency inside each of the companies and 2) do DL projects... » read more

Reduce Data Center Over-Provisioning And Stranded Capacity For Sustainability

By Hassan Moezzi - 09 Nov, 2023 - Comments: 0

In the ever-evolving landscape of data centers, the issue of stranded capacity has become a significant concern for operators. Stranded capacity refers to the underutilization of resources. It is best referred to as the elephant in the data center due to the enormity of its impact. The losses are even more significant for the enterprise data center categories at above 40%. This outcome n... » read more

Simplifying Power Module Verification Using Compliance Checking

By Wilfried Wessel - 05 Oct, 2023 - Comments: 0

By Wilfried Wessel, Siemens EDA; Simon Liebetegger, University of Applied Sciences, Darmstadt; and Florian Bauer, Siemens EDA Current simulation and verification methods for power modules are time-consuming. Each domain has specific solutions based on finite elements analysis, computational fluid dynamics and solvers for electric circuits like SPICE. This article investigates if it is possib... » read more

Gearing Up For Level 4 Vehicles

By John Koon - 05 Oct, 2023 - Comments: 0

More autonomous features are being added into high-end vehicles, but getting to full autonomy will likely take years more effort, a slew of new technologies — some of which are not in use today, and some of which involve infrastructure outside the vehicle — along with sufficient volume to bring the cost of these combined capabilities down to an affordable price point. In the meantime, ma... » read more

Everyone’s A System Designer With Heterogeneous Integration

By Ann Mutschler - 02 Oct, 2023 - Comments: 0

The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Industry Pressure Grows For Simulating Systems Of Systems

By Brian Bailey - 28 Sep, 2023 - Comments: 0

Most complex systems are designed in a top-down manner, but as the amount of electronic content in those systems increases, so does the pressure on the chip industry to provide high-level models and simulation capabilities. Those models either do not exist today, or they exist in isolation. No matter how capable a model or simulator, there never will be one that can do it all. In some cases,... » read more

When And Where To Implement AI/ML In Fabs

By Anne Meixner - 21 Sep, 2023 - Comments: 0

Deciphering complex interactions between variables is where machine learning and deep learning shine, but figuring out exactly how ML-based systems will be most useful is the job of engineers. The challenge is in pairing their domain expertise with available ML tools to maximize the value of both. This depends on sufficient quantities of good data, highly optimized algorithms, and proper tra... » read more

Designing Vehicles Virtually

By John Koon - 07 Sep, 2023 - Comments: 0

The shift toward software-defined vehicles (SDVs), electric vehicles (EVs), and ultimately autonomous vehicles (AVs) is proving the value and exposing the weaknesses in simulating individual components and complete vehicles. The ability to model this intensely complex maze of real-world interactions and possible scenarios is improving, and it's happening faster than comparable road-testing o... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.