tag: digital twins

Virtual Twins: Layers Of Challenges
By Ed Sperling - 15 Sep, 2025 - Comments: 0

Virtual twins can provide deep insights into complex systems at any point in time, but creating them requires integrating a stack of abstractions that don't naturally go together. One abstraction may be mechanical, another electrical, and the data used to create those abstraction layers needs to be fused together logically and updated over time. David Fried, corporate vice president at Lam Rese... » read more

Integrating Digital Twins on Automotive Standardized Architectures (McMaster University)
By Technical Paper Link - 10 Sep, 2025 - Comments: 0

A new technical paper titled "Engineering Automotive Digital Twins on Standardized Architectures: A Case Study" was published by researchers at McMaster Centre for Software Certification and McMaster University. Abstract "Digital twin (DT) technology has become of interest in the automotive industry. There is a growing need for smarter services that utilize the unique capabilities of DTs, r... » read more

From Data To Decisions: Exploring Enterprise Digital Thread Strategy And Simulation
By Sanjay Angadi - 17 Jul, 2025 - Comments: 0

By Sanjay Angadi and Matteo Nicolich It’s nice to think that “aha” moments come out of nowhere — that the next big thing is the result of unbridled genius (or plain dumb luck). But in reality, effective, sustainable product development rarely arises from a solitary flash of brilliance. Innovation requires information, context, collaboration, experimentation, and even failure. Usin... » read more

Addressing Silicon Lifecycle Scaling Demands
By Marc Hutner - 10 Jul, 2025 - Comments: 0

In today’s competitive business landscape, navigating complexity can be a decisive advantage, but it also presents significant challenges. Three crucial trends driving the rise of complexity are technology scaling, design scaling and system scaling. Traditionally, Design for Test (DFT) solutions have focused on the die level; however, these challenges present opportunities at the package and ... » read more

Distributing Intelligence Inside Multi-Die Assemblies
By Ed Sperling - 26 Jun, 2025 - Comments: 0

The shift from SoCs to multi-die assemblies requires more and smarter controllers to be distributed throughout a package in order to ensure optimal performance, signal integrity, and no downtime. In planar SoCs, many of these kinds of functions are often managed by a single CPU or MCU. But as logic increasingly is decomposed into chiplets, connected to each other and memories by TSVs, hybrid... » read more

EDA’s Top Execs Map Out An AI-Driven Future
By Ed Sperling - 23 Jun, 2025 - Comments: 0

Artificial intelligence is permeating the entire semiconductor ecosystem, forcing fundamental changes in AI chips, the design tools used to create them, and the methodologies used to ensure they will work reliably. This is a global race that will redefine nearly every domain over the next decade. In presentations and interviews over the past several months, top EDA executives converged on th... » read more

Simplify Simulation With Reduced-Order Modeling
By Jennifer Procario - 12 Jun, 2025 - Comments: 0

One of the biggest challenges in engineering and design is striking a balance between accuracy and speed. Development teams strive for precision but must often accelerate their simulation and computational workflows to meet production demands. Although physics-based, high-fidelity simulations are highly accurate, they are computationally expensive in terms of time and resources due to their com... » read more

From Tool Agents To Flow Agents
By Brian Bailey - 30 Apr, 2025 - Comments: 0

Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to single tool or small flows provided by a single company. What is required is a digital twin of the development process itself on which AI can operate. Semiconductor Engineering sat down with a panel of experts to discuss these issues and others, in... » read more

New Ways To Improve EDA Productivity
By Ann Mutschler - 24 Apr, 2025 - Comments: 0

EDA vendors are taking aim at new ways to improve the productivity of design and verification engineers, who are struggling to keep pace with exponential increases in chip complexity in tight time-to-market windows and with constrained engineering talent pipelines. In the past, progress often was as straightforward as improving algorithms or parallelizing computations in a linear flow. But w... » read more

Need For Speed Drives Targeted Testing
By Gregory Haley - 23 Apr, 2025 - Comments: 0

As packaging complexity increases and nodes shrink, defect detection becomes significantly more difficult. Engineers must contend with subtle variations introduced during fabrication and assembly without sacrificing throughput. New material stacks degrade signal-to-noise ratios, which makes metrology more difficult. At the same time, inspection systems face a more nuanced challenge — how t... » read more

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