Powering Efficiency: AI Transforms IC Manufacturing As ICs Fuel AI

The push to grow today’s $500 billion-plus semiconductor industry to $1 trillion in annual revenue is challenging every aspect of the broader supply chain to embrace AI.

Artificial intelligence is transforming the way fabs are architected and run, how devices are manufactured, and how server farms are constructed going forward. At the same time, all of this is being enabled by advancements in AI chips and algorithms, a virtuous cycle of smarter technology enabling other technology to improve the capabilities of both. This was the main topic of discussion at this year’s SEMICON West conference in Phoenix, driving a level of buzz that has been missing in recent years.

From a big picture standpoint, AI is creating massive opportunities everywhere. “There are $2 trillion opportunities in front of us, one presented to us by AI factories, and the other in physical AI. To capture those opportunities, innovation is required across many parts of the semiconductor design and manufacturing workloads and AI,” said Timothy Costa, general manager of industrial and computational engineering at NVIDIA. “Supercomputing and accelerated computing is here to help semiconductor design and manufacturing applications; agentic AI to increase the capability of semiconductor engineers; factory digital twins to automate fabs and fab robotics; and vision AI for better defect classification in mask and wafer inspection.”

The application of AI everywhere is just getting started. “Physical AI will transform all industries by automating the world’s millions of factories and hundreds of thousands of warehouses. Every building will become autonomous, orchestrating autonomous robots within it to capture that opportunity,” said Costa. “It’s about how we can leverage AI and accelerated computing to capture the opportunity that is presented to us with AI factories and physical AI, from accelerated semiconductor design to factory digital twins for fabs agents, which will increase the productivity of semiconductor engineers. I see opportunity in AI and ML for computational lithography, mask and wafer defect detection, and yield optimization, which are just some implementations of AI and accelerated computing that already move our industry forward.”

Costa emphasized the strategic partnership between AI infrastructure companies such as Nvidia and semiconductor equipment suppliers. “When we enter new markets we partner with those ecosystems. So we’re thrilled to see Applied Materials, Cadence, KLA, Lam Research, Siemens [EDA], and Synopsys engaging with us on accelerating the workloads of semiconductor manufacturing and design through CUDA X adoption,” he said. “We have structural analysis, we have lithography, we have discrete element methods, we have circuit simulation, we have inspection, we have CFD, and we have TCAD. We are seeing between 20X to 100X of TCAD performance boost from integration of CUDA X libraries and TCAD, for example.”

Digital twin to optimize yield
Every fraction of a percent of yield on devices can make a substantial contribution to the bottom line. This makes digital twins especially attractive because they can boost yield and shorten yield ramps. “There are several opportunities for digital twin use in high-volume manufacturing, particularly in yield optimization, said Joseph Ervin, managing director for Semiverse Products at Lam Research. “The process windows are shrinking. The integration of the process steps are challenging to achieve among patterning and shrinking structures, while more systematic defects arise alongside technology complexity and integration complexity. The patterning of atomic-level scale of structures all make it more and more challenging to achieve high yield at the leading edge and getting something that actually provides money back to companies and corporations,” said Ervin. “The key to moving very quickly up that yield ramp by solving multiple defectivity problems simultaneously.”

With existing tools, Ervin showed how virtual process modeling, virtual metrology, and virtual process optimization with design of experiments (DOEs), are revolutionizing semiconductor production. “The exciting piece involves pushing that back into this machine learning and AI to make automatic decisions based on the technology, the sensitivities, the variations, and pushing that into the technology flow. Virtual silicon requires two types of inputs — the design, essentially the features on the mask that get printed on the wafer, and the process flow (see figure 1). So looking at the process integration step-by-step, including the depositions, the etches, the cleans, the metrology, everything that’s occurring in line is done virtually. We’re able to create this structure that represents what’s happening for every part of the process line. Bringing together the virtual silicon and machine learning/AI is critical. The trick is understanding and use physics and modeling to be predictive in the process flow, and to create the actual integrated structures that are good representations of what is happening on the silicon.”

Fig. 1: Fab-centric digital twin enables yield engineers to solve multiple failure modes simultaneously rather than one by one. Source: Lam Research

AI in equipment/materials
During one of the AI panel discussions at SEMICON West, executives emphasized the need to combine technology developments with sustainability. “Everyone might have heard that OpenAI, NVIDIA and AMD made this announcement that they are going to build huge gigascale data centers with an expected power consumption of about 10 gigawatts,” said Angada Sachid, senior director and senior executive technologist at ASM. “To put that in perspective, if you take the entire Phoenix area, 10 gigawatts can power all the homes for the next 10 years, and that 10 gigawatts is only the first building block of a much larger series of data centers that are needed to enable the AI infrastructure.”

Fig. 2 (L-R): NY Creates’ Anderson, ASM’s Sachid, IBM Research’s Khare, Merck’s Matz, and TEL’s Dougherty. Source: SEMI

Multiple requirements must be met to make large data centers more efficient than they are today, just as the AI chips themselves make smarter, better design and manufacturing decisions. “Global collaboration has always been built on trust, mutual benefit, and the sheer belief that by working together we can create the greatest value for humanity,” said Tien Wu, ASE’s CEO. “Today, the semiconductor industry faces a different set of initial and boundary conditions than those encountered by our predecessors. Semiconductors are pushing the envelope of AI, and paradoxically, AI is pushing the envelope of semiconductors.”

This goes beyond just economics, though, said Wu. “It is woven into the very foundations of national security and the way humanity will thrive in the future world. Semiconductors are more than semiconductors. This new reality is intrinsically irreversible because technology itself is irreversible. In this new world, we are bound not only by supply chain efficiency and economics, but we must also be mindful of geopolitical balancing and sustainability. Over the next decade, the semiconductor industry will face growth in technology and volume, as well as increasing complexities in geographical diversity, scaling, and regulatory controls. A new level of flexibility and wisdom is required among all the challenges. However, the guiding principle remains unchanged — trust, mutual benefit, and the pursuit of creating the greatest value for mankind.”

Achieving those goals requires making AI more widely available. “Our industry is known to automate things and democratize things,” said Mukesh Khare, at IBM Research. If you look at chip design, we once designed chips by hand — literally. As design became more complex, the EDA industry abstracted out the physical aspect from hand designs to using algorithms to design chips. Today’s static algorithms are shared by designers. But with design costs at over a half a billion dollars at the 5nm node, this is the perfect time to democratize design further using AI.”

Agentic AI will be instrumental in this effort. “In the last several years, the industry has created large language models, these AI agents that will be used to design or help accelerate chip design,” Khare said. “The majority of the work is done in an open environment, and then companies can start to customize it for the use cases. We need an open ecosystem. One of the reasons the software industry has made so much progress is that everyone is contributing to accelerated software development in an open environment.”

Khare invited industry designers to participate. “This is the next step in the journey toward democratizing technology for a very broad set of companies that are trying to design chips in the leading-edge technology — really harnessing the power of collective knowledge and the agentic AI for designing chips,” he said. “For IBM, its next step involves applying agentic AI in software development, where we are getting at least a 50% improvement in productivity for the software development itself. As we apply that into our complex chip design activities, we expect at least a 50% improvement in productivity or improvement in cycle time, or you can take that in terms of cost reduction.”

Materials will play a key role in this effort, too. “Today, you can’t ask ChatGPT what is going to be the next material for semiconductor, but we do hope to build that over time,” said Laura Matz, chief science and technology officer at Merck KGaA. “But if we take a step back and look at the industry that we’re operating in today and the kind of excitement around AI, we also have to think about energy consumption. I’m based in Europe. And because a lot of the countries don’t necessarily have the energy infrastructure to serve the AI and data center demand that is being pulled on in real-time, we just opened a high-performance compute center in Munich. The acceleration in those regions is incredible, but the tap on energy efficiency is very real globally.”

Fortunately, materials development is an enabler. “In TSMC’s 2nm node you get a performance benefit, but also energy efficiency with scaling,” Matz said. “But that requires new integrations and materials developed at the atomic level. What has changed in the past couple of years is it’s not only the increasing performance requirements for the material. It’s also the speed to drive that innovation faster. So that means we have to do things differently.”

That involves breaking down some of the silos around process development and shifting to a more integrated development process. “Five years ago, we would have been looking at using AI techniques like imaging, vision, and machine learning in each individual step of the materials development process,” she said. “There are models that can go from initial materials discovery through testing and optimization within manufacturing. Those pieces are well understood. But if we optimize one step and don’t accelerate the next step, we really haven’t saved ourselves significant time. And so now the key challenge that we’re addressing is integrating all those process steps with inoperable data across steps to create a step change within materials development.”

Matz noted that it’s not clear whether a new material actually works until it’s fully processed in the fab. “We’ve been working on algorithms that can now help optimize the on-wafer results. Initial estimates show we can reduce the number of wafers required by half, which speeds the process while improving on sustainability.”

A key aspect of digital twins is whether different twins can communicate with one another. “The way that we’re conceptualizing this is to take each element of the product lifecycle, starting from concept and feasibility to early R&D, alpha and beta level, demonstration, design, control, system and software architecture, actual process demonstration and linkage with material, then moving into manufacturing in our factories,” said Mark Dougherty, president of TEL America. “As Laura mentioned, digital twin and simulation capabilities have existed for years, but the question is “How can we connect some of those together? We need to demonstrate efficiencies at each stage of the lifecycle. That includes significantly reducing the design and demonstration cycle of our equipment with help from AI.”

Conclusion
The semiconductor industry enjoys a virtual cycle of innovation between AI chips, server farms and IC fab and assembly, which is accelerating the pace of technology. Companies have made great strides in the use of digital twins, especially around areas of yield improvement and lifecycle efficiency. There is newfound drive to develop materials, equipment, processes and servers faster, while improving operating efficiencies all along the way. By building AI into the chips and the systems that process those chips, results will improve along a number of axes, each of which will feed the others.