CXL’s Protection Mechanisms And How They Handle Real-World Security Problems

A technical paper titled “How Flexible is CXL's Memory Protection?: Replacing a sledgehammer with a scalpel” was published by researchers at University of Cambridge. Abstract: "CXL, a new interconnect standard for cache-coherent memory sharing, is becoming a reality - but its security leaves something to be desired. Decentralized capabilities are flexible and resilient against malicious a... » read more

DRAM Translation Layer, Mechanism for Flexible Address Mapping and Data Migration Within CXL-Based Memory Devices

A technical paper titled “DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory” was published by researchers at Seoul National University. Abstract: "Memory disaggregation is a promising solution to scale memory capacity and bandwidth shared by multiple server nodes in a flexible and cost-effective manner. DRAM power consumption, which is reported to be... » read more

Efficiently Process Large RM Datasets In Underlying Memory Pool, Disaggregated Over CXL (KAIST)

A technical paper titled "Failure Tolerant Training with Persistent Memory Disaggregation over CXL" was published (preprint) by researchers at KAIST and Panmnesia. "TRAININGCXL can efficiently process large-scale recommendation datasets in the pool of disaggregated memory while making training fault tolerant with low overhead," states the paper. Find the technical paper here. or here (IEE... » read more