tag: double patterning

Problems Ahead For EDA
By Brian Bailey - 27 Apr, 2015 - Comments: 0

You may have discovered that the Semiconductor Engineering Knowledge Center (KC) provides various ways in which data can be viewed. One way is to see what events happened in a given year. During the 1990s, company activity in terms of new startups and acquisitions reached a peak, and in 1997 there were at least 29 startups that the KC contains and 25 companies acquired (let us know if there wer... » read more

What EDA’s Big 3 Think Now
By Ed Sperling - 23 Apr, 2015 - Comments: 0

In the past two months the CEOs of Cadence, Synopsys and Mentor Graphics delivered their annual high-level messages to their respective user groups. Semiconductor Engineering attended all of the speeches at these conferences, as it did in 2014 (see story here). From a high level, the big issues for CEOs last year were Moore's Law, the costs of design, the impact of low power, and business-... » read more

Are Three Eyes Better Than Two?
By David Abercrombie - 16 Apr, 2015 - Comments: 0

It is clear that having two eyes is better than having just one. Not only is depth perception much better, but we get to enjoy 3D movies because of it. There is also some sense of security in knowing that if something terrible happened to one eye, you always have a backup. Have you ever wondered if these sorts of advantages are extendable? You’ve probably heard the phrase about someone ha... » read more

Big Changes At 10nm And Beyond
By Ed Sperling - 16 Apr, 2015 - Comments: 0

The move to 16/14nm finFETs is relatively straightforward. The move to 10nm and 7nm will be quite different. While double patterning with colors at 16/14nm has a rather steep learning curve, reports from chipmakers developing advanced chips is the technology and methodologies are manageable once engineering teams begin working with it. The hardest part is visualizing how different parts will... » read more

Signal Integrity Issues
By Ed Sperling - 21 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss signal integrity with Rob Aitken, research fellow at [getentity id="22186" comment="ARM"]; PV Srinivas, senior director of engineering for the Place & Route Division of [getentity id="22017" e_name="Mentor Graphics"]; and Bernard Murphy, chief technology officer at [getentity id="22026" e_name="Atrenta"]. What follows are excerpts of that conver... » read more

Industry Scorecard For 2014
By Brian Bailey - 22 Dec, 2014 - Comments: 0

At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Part one addressed the market and semiconductor areas and in thi... » read more

EDA Vendors Prepare For 7nm
By Ann Mutschler - 18 Sep, 2014 - Comments: 0

It’s not too early to begin looking at design tools for the 7nm, even though the node is not expected to be production-ready until later this decade. While still in the early stages, foundries already in development with leading EDA companies, even though the water remains murky at this point. “7nm right now is in early definition, so we don't know exactly what it will be,” observed... » read more

IP Integration Challenges Rising
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

It’s not just [getkc id="80" comment="lithography"] that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers. Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of ... » read more

DFM And Multipatterning
By Ed Sperling - 17 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss DFM at advanced nodes with Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics; Jongwook Kye, lithography modeling and architecture fellow at GlobalFoundries; David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics; Ya-Chieh Lai, engineering director for DFM/CLS silicon signoff and ver... » read more

DFM And Multipatterning
By Ed Sperling - 03 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss DFM at advanced nodes with Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics; Jongwook Kye, lithography modeling and architecture fellow at GlobalFoundries; David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics; Ya-Chieh Lai, engineering director for DFM/CLS silicon signoff and ver... » read more

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