What EDA’s Big 3 Think Now

One year later, the conversation has shifted for all three CEOs.


In the past two months the CEOs of Cadence, Synopsys and Mentor Graphics delivered their annual high-level messages to their respective user groups. Semiconductor Engineering attended all of the speeches at these conferences, as it did in 2014 (see story here).

From a high level, the big issues for CEOs last year were Moore’s Law, the costs of design, the impact of low power, and business-related concerns. This year, the big issues were Moore’s Law (process challenges), security, software and business-related concerns such as time to market.

Lip-Bu Tan, president and CEO of Cadence, and Aart de Geus, chairman and co-CEO of Synopsys, focused their keynotes this year on technology issues that have been getting more problematic over the past couple of process nodes—process challenges, IP and software. Wally Rhines, chairman and CEO of Mentor Graphics, took a different tack, focusing entirely on security threats and what will be required for hardware as everything becomes connected to everything else.

Process challenges
One of the biggest issues being faced by chipmakers these days involves the continuation of Moore’s Law. While it’s technically possible to shrink features all the way down to 1.5nm, the economics for doing so are changing. As a result, some companies are pausing before moving to the next node, or have plans to stay put at 28nm—the last node before Double Patterning and the transition to finFETs begin raising the cost per gate.

STMicroelectronics, for example, is focused on FD-SOI at 28nm, including forward and back biasing, with another shrink ahead at some future date. (Timing of the next node is uncertain.) Yet others are pushing forward into finFETs, including FPGA companies and IDMs such as Samsung, Intel Corp., and large fabless companies such as Qualcomm.

De Geus believes the road is clear all the way to 5nm, which is probably about five years or more away. “We can simulate in 3D at 5nm,” said De Geus at the Synopsys User Group. “Five years ago, the whole notion of finFETs fell into two camps. One said it would never happen. The other said it would.”

He noted that the increase in design rules and double patterning turned out to be minor blips that are being handled quite effectively by existing tools. “Double patterning is a fundamental requirement for some layers,” said de Geus. “But from a design point of view, we have completely hit this.”

Tan, while optimistic about continuing to shrink features at the leading edge of design, said there are challenges that need to be resolved. “With 10nm, metal 1 will require triple patterning. And at 7nm to 8nm, there are a lot of challenges.”

This is largely consistent with presentations by all of the Big Three leaders last year. De Geus predicted at SNUG 2014 there would be at least six more years of Moore’s Law, while Tan said at CDNLive 2014 that system-in-package and stacked die will play a stronger role. And at U2U 2014, Rhines said shrinking features won’t be the best way to progress, indicating that bio switches and carbon nanotubes will be required.

Mentor’s Rhines came out forcefully this year on the need for semiconductor security, breaking out the threats into three distinct areas: side channel attacks, counterfeit chips, and malicious logic such as Trojans.

“In EDA, most of the effort—60% to 70%—is spent on verifying the chip does what it’s supposed to do,” said Rhines. “The bigger challenge is making the sure the chip doesn’t do what it’s not supposed to do.”

He said that until now the threats have been largely ignored by chipmakers because they add to the development cost. “The number one concern is embedded hardware Trojans. They are very difficult to detect, and the state spaces on a complex chip are too extensive to vigorously analyze. The cost of test is not cheap. But the biggest problem is testing for unknown unknowns. The primary sources of that are IP embedded in a chip, scripts to synthesize something, or IP that has been purchased. The threat is in the design phase, where you can insert run-time detection or a co-processor that operates at run-time and looks at the transactions in an embedded CPU.”

That makes it an EDA problem, as well as an opportunity for tools developers. De Geus noted the growing security issue, as well, pointing to a couple of areas in particular. “It’s a silicon to software to security continuum,” he said, adding that the automotive market is a second critical area for security. “Auto standards are being created to minimize the risk. This came from qualification of what are now highly synthesized die.”

Cadence has been actively involved in security, as well, a position that has been bolstered by its acquisition of Jasper last year.

All three EDA leaders flagged software and IP as a critical area this year. Cadence’s Tan cited software challenges and a surge in IP that needs to be integrated into complex SoCs. “There are a lot of IP blocks,” he said, including interface and specialty IP. “And there will be exponential growth at 16 and 14nm.”

He said IP will be the basis of much of the Internet of Things, including vision processing and sensor fusion, but that the cost of IP will increase as characterization increases. “There will be more cells and more PVT (process/voltage/temperature) corners as we move down geometries.”

Tan also noted that vertical aggregation is beginning to occur inside large companies as they combine IP, chips, firmware, drivers, operating systems, middleware and applications. “There is a 360-degree change happening,” he said, pointing to a shift toward more software, flexible PCBs, the need to address power and thermal issues, and the push into 2.5D and 3D packaging.

Along the same lines, de Geus said that IP needs to be silicon proven, with more investment in subsystems, IP prototyping kits and software modules for rapid prototyping. “Shift left implies that everything needs to move to the left, including debug and coverage, static and formal, AMS, VIP and simulation and emulation. And we need faster engines for everything.”

In keeping with his focus on security, Rhines believes future IP will be hardened to prevent tampering—particularly after some highly publicized future attacks. But he also said there will need to be a big push to control counterfeit components, noting that an estimated. 0.5% to 35% of incoming products are suspected of being counterfeit, and many of them are sold to independent distributors. “Dell issued a recall of motherboards with a virus,” he said.

What’s changed
So how do these messages compare with last year’s speeches to users of EDA tools? For one thing, cost is still a big issue, but at the leading edge no one is addressing it directly. The arguments that Moore’s Law works as an economic formula ended at 28nm, and while there is much that can be done to speed time to market and reduce the number of re-spins, it will still cost more per gate at 16/14nm than at 28nm.

Second, while power is still the big gating factor in designs—particularly in such markets as mobile or high-end servers—that message has been received loud and clear by chipmakers. If a chipmaker can’t meet the power budget it doesn’t win the socket, and if an end device can’t hold a charge long enough then it’s not likely to win over the consumer.

Third, while last year the focus of keynote speeches was on business and EDA’s growth, the Big Three EDA vendors are not just EDA companies anymore. Synopsys has moved heavily into IP and software, Cadence is now invested heavily in IP, and Mentor has shifted into wiring harnesses, computation fluid dynamics, software and, presumably, will be focusing heavily on security in the future.

The shifts in focus are subtle, and seemingly significant, but it will take another year of comparisons to really chart just how much the messages have changed.