Cost Per Transistor Gets Fuzzier

By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ed Sperling Cost per transistor always has been a major reason for chipmakers to migrate to the next process node. By shrinking transistors and adding more logic, performance usually gets a boost. Moreover, that usually provides enough engineering wiggle room to add some improvements in energy efficiency. The basic assumption that you can double the number of transistors every 24 months,... » read more

Hospital Privileges

By David Abercrombie - 24 Jan, 2013 - Comments: 0

By David Abercrombie In our double patterning (DP) conversations so far, we’ve discussed what it means to decompose a single layer into two masks, and identified typical configurations of polygons that can cause DP violations. We specifically discussed the most common odd cycle violations, and how to fix them by increasing the spaces between polygons. The reality, though, is that no matter h... » read more

Tradeoffs On The Fly

By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler With classical bulk planar technology no longer shrinkable, the industry has been honing in on new ways to continue some scaling, achieve extra speed or better power while minimizing leakage. “To overcome the limits [of bulk planar technology] we need a different solution,” explained Giorgio Cesano, technology R&D marketing director at STMicroelectron... » read more

Too Many Rules

By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Ed Sperling The number of restrictive design rules that have to be dealt with by routers at 28nm and beyond has increased by several orders of magnitude compared with several generations ago, creating havoc in the automated tools world and slowing down the entire design process. At a time when market windows are shrinking, complexity is making it harder to meet even the old schedules. Th... » read more

DFM Challenges Abound Below 20nm

By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler As semiconductor design teams struggle to wring the last few percentage of die shrink from a technology node, much of the ability to do that rests on the EDA tools. From place and route through DFM checks—essentially, everything that happens before the design is sent to the fab or foundry—it all must be tightly integrated with the manufacturing process so it co... » read more

Double Patterning From Design Enablement To Verification

By Various Writers - 13 Dec, 2012 - Comments: 0

Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges they present, and various solutions, including: DP design methodologies, current DP conflict feedback mechanisms, and how they can help designers identify and resolve conflicts. E... » read more

Increasing Levels Of Risk

By Ed Sperling - 13 Dec, 2012 - Comments: 0

Semiconductor Manufacturing & Design sits down with Mentor Graphics' Jean-Marie Brunet to talk about double patterning, finFETs, design rules at advanced nodes and why design for manufacturing (DFM) has suddenly become so popular. [youtube vid=3GHvikyjZow] » read more

Why Do My DP Colors Keep Changing?

By David Abercrombie - 15 Nov, 2012 - Comments: 0

By David Abercrombie At 20nm, foundries are using several different double patterning design flows. One of the more common flows does not actually require the design team to decompose their layers into two colors. The designer only has to verify that the design can be decomposed before taping out each single layer. There are certain obvious advantages to this flow. For example, the designer do... » read more

Behind The Mask

By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss the current and future photomask manufacturing challenges with Franklin Kalk, executive vice president and chief technology officer at Toppan Photomasks, one of the world’s largest merchant mask makers. SMD: The outlook for the photomask industry is for 2% growth in 2012. Do you agree with that? Kalk: That’s ... » read more

Inflection Points Ahead

By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Engineering challenges have existed at every process node in semiconductor designs, but at 20nm and beyond, engineers and executives on all sides of the industry are talking about inflection points. An inflection point is literally the place where a curve on a graph turns down or up, but in the semiconductor industry it’s usually associated with the point at which a progres... » read more

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tag: double patterning

Cost Per Transistor Gets Fuzzier

Hospital Privileges

Tradeoffs On The Fly

Too Many Rules

DFM Challenges Abound Below 20nm

Double Patterning From Design Enablement To Verification

Increasing Levels Of Risk

Why Do My DP Colors Keep Changing?

Behind The Mask

Inflection Points Ahead

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