tag: DRAM

Memory’s Future Hinges On Reliability
By Karen Heyman - 14 Feb, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the impact of power and heat on off-chip memory, and what can be done to optimize performance, with Frank Ferro, group director, product management at Cadence; Steven Woo, fellow and distinguished inventor at Rambus; Jongsin Yun, memory technologist at Siemens EDA; Randy White, memory solutions program manager at Keysight; a... » read more

Enabling Beyond-Bound Decoding For DRAM By Unraveling Reed-Solomon Codes
By Technical Paper Link - 06 Feb, 2024 - Comments: 0

A technical paper titled “Unraveling codes: fast, robust, beyond-bound error correction for DRAM” was published by researchers at Rambus. Abstract: "Generalized Reed-Solomon (RS) codes are a common choice for efficient, reliable error correction in memory and communications systems. These codes add 2t extra parity symbols to a block of memory, and can efficiently and reliably correct up ... » read more

How To Stop Row Hammer Attacks
By Ed Sperling - 30 Jan, 2024 - Comments: 0

Row hammer is a well-publicized target for cyberattacks on DRAM, and there have been attempts to stop these attacks in DDR4 and DDR5, but with mixed results. The problem is that as density increases, distance decreases, making it more likely that flipped bit cell in one row can disturb a bit cell in another, and that bits flipped across an entire row can flip another row. Steven Woo, fellow and... » read more

What’s Changing In DRAM
By Ed Sperling - 22 Jan, 2024 - Comments: 0

More data requires more processing and more storage, because that data needs to be stored somewhere. What’s changing is that it’s no longer just about SRAM and DRAM. Today, multiple types of DRAM are used in the same devices, each with its own set of tradeoffs. C.S. Lin, marketing executive at Winbond, talks about the potential problems that causes, including mismatches in latency, and high... » read more

How Is The Chip Industry Really Doing?
By Ed Sperling - 17 Jan, 2024 - Comments: 2

Throughout 2023, the general consensus among chip industry watchers was that IC sales were flat to down, fueled by market saturation for smart phones and PCs and excess inventory and capacity in DRAM and flash. But that doesn't tell the whole story, which is becoming highly nuanced and complicated. Unlike in the past, understanding how the chip industry is faring is no longer a simple math f... » read more

The Future Of Memory
By Karen Heyman - 11 Jan, 2024 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to talk about the impact of off-chip memory on power and heat, and what can be done to optimize performance, with Frank Ferro, group director, product management at Cadence; Steven Woo, fellow and distinguished inventor at Rambus; Jongsin Yun, memory technologist at Siemens EDA; Randy White, memory solutions program manager at Keysight; a... » read more

Scaling Server Memory Performance To Meet The Demands Of AI
By Tim Messegee - 11 Jan, 2024 - Comments: 0

AI, whether we’re talking about the number of parameters used in training or the size of large language models (LLMs), continues to grow at a breathtaking rate. For over a decade, we’ve witnessed a 10X per year scaling. It’s a growth rate that puts pressure on every aspect of the computing stack: processing, memory, networking, you name it. The platform vendors are responding to the in... » read more

SRAM’s Role In Emerging Memories
By Karen Heyman - 05 Jan, 2024 - Comments: 1

Experts at the Table — Part 3: Semiconductor Engineering sat down to talk about AI, the latest issues in SRAM, and the potential impact of new types of memory, with Tony Chan Carusone, CTO at Alphawave Semi; Steve Roddy, chief marketing officer at Quadric; and Jongsin Yun, memory technologist at Siemens EDA. What follows are excerpts of that conversation. Part one of this conversation can be ... » read more

Efficient LLM Inference With Limited Memory (Apple)
By Technical Paper Link - 04 Jan, 2024 - Comments: 0

A technical paper titled “LLM in a flash: Efficient Large Language Model Inference with Limited Memory” was published by researchers at Apple. Abstract: "Large language models (LLMs) are central to modern natural language processing, delivering exceptional performance in various tasks. However, their intensive computational and memory requirements present challenges, especially for device... » read more

Package Propagation Delay Dependency Of Advanced Fly-By Routing For Next Generation DDR5
By Rambus - 03 Jan, 2024 - Comments: 0

Package signal transit delay is an important parameter for high-speed designs like DDR5. Package delay along with PCB delay dictates the data rates of DDR5 interface running at 4.0 Gbps and beyond. From DDR3 (third generation DDR) onwards, daisy chain routing has been widely used as it can support high data rate operations by providing smaller trace stubs and capacitive loadings. Even so, beyon... » read more

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