tag: DRAM

Smaller Geometries, Bigger Demands: The Role Of OCD In GAA Logic And Vertical Gate DRAM Process Control
By Jiangtao Hu - 09 Dec, 2025 - Comments: 0

AI workloads are pushing the boundaries of compute, memory, and interconnect architectures, and to meet these goals, manufacturers are rapidly accelerating advanced logic and DRAM development. Chief among these innovations: gate-all-around (GAA) logic transistor and vertical gate (VG) DRAM, two device architectures that promise higher performance, improved power efficiency, and greater scalabil... » read more

Enhancing CMP Process Control with Intelligent Line Monitoring & Integrated Metrology
By Onto Innovation - 09 Dec, 2025 - Comments: 0

New logic transistor designs, 3D NAND stacking, and DRAM integration introduce more CMP layers and tighter process windows. Traditional metrology approaches struggle to keep pace, especially with the need for high sampling rates, multiple control zones, and improved signal-to-noise ratios. Onto Innovation’s Intelligent Line Monitoring & Control with Integrated Metrology offers a new appro... » read more

Boosting Memory Bandwidth Availability By Salvaging Idle I/O Bandwidth Resources (Georgia Tech)
By Technical Paper Link - 03 Dec, 2025 - Comments: 0

A new technical paper titled "Pushing the Memory Bandwidth Wall with CXL-enabled Idle I/O Bandwidth Harvesting" was published by researchers at Georgia Institute of Technology. Abstract "The continual increase of cores on server-grade CPUs raises demands on memory systems, which are constrained by limited off-chip pin and data transfer rate scalability. As a result, high-end processors ty... » read more

Multi-Core Architecture Optimized For Time-Predictable Neural Network Inference (FZI, KIT)
By Technical Paper Link - 21 Nov, 2025 - Comments: 0

A new technical paper titled "MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference" was published by researchers at FZI Research Center for Information Technology and Karlsruhe Institute for Information Technology (KIT). Abstract: "Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural network... » read more

A Decade Of Architectural RowHammer Defense Solutions (Meta, SNU, UIUC)
By Technical Paper Link - 19 Nov, 2025 - Comments: 0

A new technical paper titled "SoK: Systematizing a Decade of Architectural RowHammer Defenses Through the Lens of Streaming Algorithms" was published by researchers at Meta, Seoul National University and University of Illinois at Urbana-Champaign. Abstract: "A decade after its academic introduction, RowHammer (RH) remains a moving target that continues to challenge both the industry and aca... » read more

Research Bits: Nov. 10
By Jesse Allen - 10 Nov, 2025 - Comments: 0

Post-doping plasma for DRAM capacitors Researchers from Ulsan National Institute of Science and Technology (UNIST), Pohang University of Science and Technology (POSTECH), and Seoul National University of Science and Technology developed a post-doping plasma (PDP) process to improve the performance of DRAM capacitors. Aluminum-doped titanium dioxide (Al-doped TiO2) is a promising material fo... » read more

Algorithm–HW Co-Design Framework for Accelerating Attention in Large-Context Scenarios (Cornell)
By Technical Paper Link - 07 Nov, 2025 - Comments: 0

A new technical paper titled "LongSight: Compute-Enabled Memory to Accelerate Large-Context LLMs via Sparse Attention" was published by researchers at Cornell University. Abstract "Large input context windows in transformer-based LLMs help minimize hallucinations and improve output accuracy and personalization. However, as the context window grows, the attention phase increasingly dominates... » read more

LPDDR6: Not Just For Mobile Anymore
By Ed Sperling - 03 Nov, 2025 - Comments: 0

LPDDR memory has been almost synonymous with mobile devices, but starting with the new LPDDR6 specification released in July 2025 by JEDEC, it will begin showing up inside of data centers, as well, early next year. The key factors in various flavors of DRAM are bandwidth, capacity, and cost. HBM is the fastest, but it's also expensive, and it requires a 2.5D or 3.5D packaging approach. GDDR is ... » read more

In-DRAM TRNG Using Simultaneous Multiple-Row Activation (ETH Zurich, CISPA)
By Technical Paper Link - 31 Oct, 2025 - Comments: 0

A new technical paper titled "In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips" was published by researchers at ETH Zürich and CISPA. Abstract "In this work, we experimentally demonstrate that it is possible to generate true random numbers at high throughput and low latency in commercial off-the-shelf (COTS) DRAM chi... » read more

Performance Of A Memory System With FeRAM vs. DRAM (Georgia Tech, Imec, NTUA)
By Technical Paper Link - 29 Oct, 2025 - Comments: 0

A new technical paper titled "Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model" was published by researchers at Georgia Tech, imec and National Technical University of Athens. Abstract "We present a framework for design technology co-optimization (DTCO) of the main memory system with one transistor-one capacitor (1T1C) ferroelectric random access memory (FE... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy