Critical Factors For Storing Data In DRAM


DRAM is becoming more complicated to develop, and more difficult to manage inside AI data centers. In the past, latency, bandwidth, and capacity were the primary considerations. But as the amount of data that needs to be processed, moved, and stored continues to rise, a whole new set of factors is emerging. Steven Woo, fellow and distinguished inventor at Rambus, talks about latency under load,... » read more

Understanding and Mitigating Column-Based Read Disturbance in DRAM Chips (ETH Zurich, CISPA)


A new technical paper titled "ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems" was published by researchers at ETH Zurich and CISPA. Abstract "We experimentally demonstrate a new widespread read disturbance phenomenon, ColumnDisturb, in real commodity DRAM chips. By repeatedly opening or keeping a DRAM row (aggressor row) ope... » read more

Algorithms For Black-Box, Physical-to-DRAM Address-Mapping Recovery (Georgia Tech, CNRS, Et Al.)


A new technical paper titled "Knock-Knock: Black-Box, Platform-Agnostic DRAM Address-Mapping Reverse Engineering" was published by researchers at Georgia Tech, ESILV, CentraleSupelec, Inria, CNRS, IRISA. Abstract "Modern Systems-on-Chip (SoCs) employ undocumented linear address-scrambling functions to obfuscate DRAM addressing, which complicates DRAM-aware performance optimizations and hind... » read more

Semiconductor Metrology: IMMSE For The Rapid ID of Defective Chips (Samsung)


A new technical paper titled "Ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry for semiconductor metrology" was published by researchers at Samsung. Abstract "We propose an ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry (IMMSE) system for semiconductor metrology. The IMMSE system achieves large-area measurements with a 20 mm × 20 mm field of ... » read more

Cost-Effective, Orthogonal Approach to Resilient Memory Design (Univ. of Central Florida, UT San Antonio, Rochester)


A new technical paper titled "SCREME: A Scalable Framework for Resilient Memory Design" was published by researchers at University of Central Florida, University of Texas at San Antonio and University of Rochester. Abstract "The continuing advancement of memory technology has not only fueled a surge in performance, but also substantially exacerbate reliability challenges. Traditional soluti... » read more

LPDDR: A Versatile Memory Powering The Next Wave Of Mobile, Edge & Endpoint Computing


The world of computing is evolving at a breakneck pace. From smartphones and ultra-thin laptops to autonomous vehicles and edge AI devices, the demand for memory that balances performance, power efficiency, and compact form factors has never been greater. This shift is driven by a few undeniable trends, including the increased deployment of AI models across verticals at the edge and higher us... » read more

HBM4 Memory: Break Through to Greater Bandwidth


Delivering unrivaled memory bandwidth in a compact, high-capacity footprint, has made HBM the memory of choice for AI training. HBM4 is the fourth major generation of the HBM standard, with new power management and RAS features. The Rambus HBM4 Controller provides industry-leading performance to 10.0 Gb/s, enabling a memory throughput of over 2.5 TB/s for training systems, generative AI and oth... » read more

The Evolution of DRAM


DRAM has been around since 1966, but today it's still the same basic 1T 1C bit cell architecture. Yet changes are coming as DRAM is called upon to store and retrieve more data faster. Steve Woo, distinguished inventor and fellow at Rambus, talks about how DRAM works, why there are different flavors, the impact of cooling new solutions in denser configurations, and ongoing issues involving the s... » read more

A Fundamental Rethinking Of Memory Hierarchy Design (Stanford University)


A new technical paper titled "The Future of Memory: Limits and Opportunities" was published by researchers at Stanford University and an independent researcher. Abstract "Memory latency, bandwidth, capacity, and energy increasingly limit performance. In this paper, we reconsider proposed system architectures that consist of huge (many-terabyte to petabyte scale) memories shared among large ... » read more

Tools, Models and System Support for PIM Architectures, With DRAM-Focus (ETH Zurich)


A new technical paper titled "New Tools, Programming Models, and System Support for Processing-in-Memory Architectures" was published by researchers at ETH Zurich. Abstract "Our goal in this dissertation is to provide tools, programming models, and system support for PIM architectures (with a focus on DRAM-based solutions), to ease the adoption of PIM in current and future systems. To this ... » read more

← Older posts Newer posts →