tag: DRAM

Dynamic KV Cache Scheduling in Heterogeneous Memory Systems for LLM Inference (Rensselaer Polytechnic Institute, IBM)
By Technical Paper Link - 28 Aug, 2025 - Comments: 0

A new technical paper titled "Accelerating LLM Inference via Dynamic KV Cache Placement in Heterogeneous Memory System" was published by researchers at Rensselaer Polytechnic Institute and IBM. Abstract "Large Language Model (LLM) inference is increasingly constrained by memory bandwidth, with frequent access to the key-value (KV) cache dominating data movement. While attention sparsity red... » read more

Scaling DRAM Technology To Meet Future Demands: Challenges And Opportunities
By Rambus - 13 Aug, 2025 - Comments: 0

Since the invention of the 1T1C bit cell more than 50 years ago, DRAMs have become the main memory of choice for processors in computer systems and many consumer electronics devices. As new use computing paradigms have been created, including 3D graphics, cloud computing, smart phones, and AI processing, specialized processors and DRAM memories have been developed that are optimized for these u... » read more

LtRAM And StRAM: Specialized Memory Architectures Leveraging Workload-Specific Access Characteristics (Stanford, Microsoft)
By Technical Paper Link - 12 Aug, 2025 - Comments: 0

A new technical paper titled "Towards Memory Specialization: A Case for Long-Term and Short-Term RAM" was published by researchers at Stanford University and Microsoft, and an independent researcher. Abstract "Both SRAM and DRAM have stopped scaling: there is no technical roadmap to reduce their cost (per byte/GB). As a result, memory now dominates system cost. This paper argues for a parad... » read more

What’s Different About HBM4
By Ed Sperling - 11 Aug, 2025 - Comments: 0

Memory bandwidth is limiting the flow of huge datasets that are needed to train AI models. There is much more data to process, store, and retrieve, but the speed at which that data moves through high-bandwidth memory (HBM) stacks is significantly lower than the speed at which data can be processed. Frank Ferro, group director for product management at Cadence, talks about the new HBM4 standard,... » read more

Epitaxial Growth Of Up To 120 Si/SiGe Bilayers In View of 3D DRAM Applications (imec, Ghent Univ.)
By Technical Paper Link - 05 Aug, 2025 - Comments: 0

A new technical paper titled "Epitaxial growth of up to 120× {Si0.8Ge0.2/Si} bilayers in view of three dimensional dynamic random access memory applications" was published by researchers at imec and Ghent University. Abstract "Epitaxially grown Si/Si1−xGex multi-stacks with ≥100 bilayers (≥200 sublayers) are being considered for three dimensionally vertically stacked dynamic rando... » read more

LLM Inference: Core Bottlenecks Imposed By Memory, Compute Capacity, Synchronization Overheads (NVIDIA)
By Technical Paper Link - 01 Aug, 2025 - Comments: 0

A new technical paper titled "Efficient LLM Inference: Bandwidth, Compute, Synchronization, and Capacity are all you need" was published by NVIDIA. Abstract "This paper presents a limit study of transformer-based large language model (LLM) inference, focusing on the fundamental performance bottlenecks imposed by memory bandwidth, memory capacity, and synchronization overhead in distributed ... » read more

Rowhammer Attack On NVIDIA GPUs With GDDR6 DRAM (University of Toronto)
By Technical Paper Link - 16 Jul, 2025 - Comments: 0

A new technical paper titled "GPUHammer: Rowhammer Attacks on GPU Memories are Practical" was published by researchers at University of Toronto. Abstract: "Rowhammer is a read disturbance vulnerability in modern DRAM that causes bit-flips, compromising security and reliability. While extensively studied on Intel and AMD CPUs with DDR and LPDDR memories, its impact on GPUs using GDDR memorie... » read more

Stacking Persistent Embedded Memories Based On Oxide Transistors Upon GPGPU Platforms (Georgia Tech)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms" was published by Georgia Tech. Abstract "In contemporary general-purpose graphics processing units (GPGPUs), the continued increase in raw arithmetic throughput is constrained by the capabilities of the register file (single-cycle) and last-level cache (high bandwidth... » read more

Novel Assembly Approaches For 3D Device Stacks
By Laura Peters - 30 Jun, 2025 - Comments: 0

The next big leap in semiconductor packaging will require a slew of new technologies, processes, and materials, but collectively they will enable orders of magnitude improvement in performance that will be essential for the AI age. Not all of these issues are fully solved but the recent Electronic Components Technology Conference (ECTC) provided a glimpse into the huge leaps in progress that... » read more

The Best DRAMs For Artificial Intelligence
By Bryon Moyer - 12 Jun, 2025 - Comments: 0

Artificial intelligence (AI) involves intense computing and tons of data. The computing may be performed by CPUs, GPUs, or dedicated accelerators, and while the data travels through DRAM on its way to the processor, the best DRAM type for this purpose depends on the type of system that is performing the training or inference. The memory challenge facing engineering teams today is how to keep... » read more

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