Catching Critical Defects In TSVs And Stacked Chips


Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect capture rate and distinguishing between yield-killing and false positives. New methods for interconnecting devices using through-silicon vias (TSVs) and hybrid bonding in stac... » read more

Cryogenic Etch: A Key Enabler Of 3D NAND


Increased storage needs at the edge and in the cloud are fueling rising demand for higher-capacity flash memory across multiple applications. Released every 12 to 18 months, 3D NAND scaling outpaces most other semiconductor devices in replacement rate and performance gains. With each new generation, NAND suppliers deliver 50% faster read/write speeds, 40% greater bit density, lower latency, ... » read more

What’s Next For Through-Silicon Vias


From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process


Abstract "With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and sol... » read more

Effective Post-TSV-DRIE Wet Clean Process For Through Silicon Via Applications


Deep Reactive Ion Etch (DRIE) processes used to form through silicon vias (TSVs) achieve high aspect ratios by depositing polymer on the vertical sidewalls of the features. This polymer material must be removed before other materials (including dielectric liner, Cu barrier, and Cu) are deposited in the TSVs. Clean processes adapted from Cu damascene integration flows use a combination of oxygen... » read more