tag: DVFS

DVFS On The Sidelines
By Brian Bailey - 13 Aug, 2015 - Comments: 2

Power reduction is one of the most important aspects of chip design these days, but not all power reduction techniques are used equally. Some that were once important are fading and dynamic voltage, and frequency scaling (DVFS) is one of them. What's changed, and will we see a resurgence in the future? What is it? DVFS has physics powerfully in its favor. As Vinod Viswanath, director of res... » read more

How Hard Is FD-SOI Design?
By Ann Mutschler - 21 May, 2015 - Comments: 0

Fully-depleted silicon-on-insulator ([getkc id="220" kc_name="FD-SOI"]) manufacturing technology reached of point of readiness for mass production at the end of March. Along with that, it’s now clear that while there are some impacts on the design flow, those impacts are not game changers. For one thing, the tools required are the same ones currently used for 28nm planar bulk CMOS. The onl... » read more

With Responsibility Comes Power
By Brian Bailey - 12 Feb, 2015 - Comments: 0

The debate continues as to whether [getkc id="106" kc_name="power"] has risen to become a primary design consideration, or if it remains secondary to functionality and performance. What is indisputable is the rise in the importance of both power and energy conservation. As technology improves, additional aspects of the design flow are being affected. With that, the focus for power reduction is ... » read more

(Low) Power Predictions 2015
By Anand Iyer - 15 Jan, 2015 - Comments: 1

Happy New Year! As we step into the New Year, lots of exciting things are already underway. First of all, the Internet of Things (IoT) is shaping up in a big way as witnessed at CES last week. Advances in devices that can talk to each other and share information are becoming a reality. Automotive applications, medical devices, industry automation, energy distribution and entertainment are all a... » read more

Problems Lurk In SoC Boundaries
By Brian Bailey - 04 Dec, 2014 - Comments: 0

Interfaces always have been a problem, because only rarely does anyone have responsibility for them. Responsibilities generally are tied to functional blocks with the prevailing notion that if all blocks do the right thing, they will also behave correctly when brought together. Design teams that believe this eventually find out the fallacy of this assumption. To make matters worse, these are of... » read more

User Case Study
By Joseph Hupcey III - 06 Nov, 2014 - Comments: 0

Whenever more than one clock is employed in an SoC (which is all SoCs), the risk of errors from clock domain crossings (CDC) – signals (or groups of signals) that are generated in one clock domain and consumed in another – is incredibly high. Unfortunately, CDC bugs are nearly impossible to catch with conventional simulations. Thus, all too often they escape into silicon. Debugging them in ... » read more

After Moore’s Law: More With Less
By Brian Bailey - 10 Jul, 2014 - Comments: 6

In the decades when Moore’s Law went unquestioned, the industry was able to migrate to the next smaller node and receive access to more devices that could be used for increased functionality and additional integration. While less significant transistor-level power savings have been seen from the more recent nodes, as leakage currents have increased, the additional levels of integration have b... » read more

Making Modeling Less Unpleasant
By Brian Bailey - 19 Dec, 2013 - Comments: 1

How many times did your mother tell you to take your medicine? You knew two things: a) it would be unpleasant and b) it would be worth the few seconds of unpleasantness because of the benefits it would provide. It appears as if the electronics industry has the same issue with modeling. We talk about the benefits that having a system-level model would have — the ability to explore system archi... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 16 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate ap... » read more

Trading Off Power And Performance
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler There is no shortage of opinions when it comes to the topic of performance and power tradeoffs. From abstracting the task from engineers to process considerations, engineering teams have a number of tools and approaches at their disposal to make the optimal design choices for their application. Take the MCU application space for instance. Ken Dwyer, director of app... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy