tag: e

Universal Verification Methodology Running Out Of Steam
By Ann Mutschler - 30 Jul, 2020 - Comments: 2

For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, more complex, and significantly larger, UVM is running out of steam. Consensus is building that some fundamental changes are required, moving tools up a level of abstraction and making them more ag... » read more

Shrinking AV’s 1 Billion Test Miles
By Kevin Fogarty - 08 Oct, 2019 - Comments: 0

There is still no answer to how many miles an autonomous vehicle needs to drive before it's proven safe. But some AV developers and test companies are hoping to ease the burden a bit with automation that makes millions of real and simulated miles of road testing simpler to implement, supported by standards that make it easier to create and trade simulation scenarios. The goal is to reduce th... » read more

How Much Verification Is Necessary?
By Ann Mutschler - 27 Jul, 2017 - Comments: 0

Since the advent of IC design flows, starting with RTL descriptions in languages like Verilog or VHDL, project teams have struggled with how much verification can and should be performed by the original RTL developers. Constrained-random methods based on high-level languages such as [gettech id="31021" t_name="e"] or [gettech id="31023" comment="SystemVerilog"] further cemented the role of t... » read more

Poised For Aspect-Oriented Design?
By Brian Bailey - 13 Aug, 2015 - Comments: 8

In 1992, [getperson id=" 11046 " comment="Yoav Hollander"] had the idea to take a software programming discipline called aspect-oriented programming (AOP) and apply it to the verification of hardware. Those concepts were incorporated into the [gettech id="31021" t_name="e"] language and [getentity id="22068" e_name="Verisity"] was formed to commercialize it. Hollander had seen that using obj... » read more

The Problem With EDA Standards
By Brian Bailey - 07 Nov, 2013 - Comments: 0

In the EDA industry, does standard mean the same as it does in most industries? The Free Dictionary defines it as: Something, such as a practice or a product, that is widely recognized or employed, especially because of its excellence. In the EDA industry, a standards body is the place where EDA companies and customers come together to try and bring about convergence, often in a new or emerging... » read more

Interface Additions To The e Language For Effective Communication With SystemC TLM 2.0 Models
By Various Writers - 23 Aug, 2012 - Comments: 0

The last several years have seen strong adoption of transaction-level models using SystemC TLM 2.0. Those models are used for software validation and virtual prototyping. For functional verification, TLMs have a number of advantages—they are available earlier, they allow usersto divide their focus on verifying functionality and protocol/timing details, they enable higher level reuse, and they... » read more

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