tag: ECO

Golden Signoff ECO For Last-Mile Electronic Design Closure
By Manoj Chacko - 03 Oct, 2022 - Comments: 0

Electronic design developers really hate iterative, resource-intensive tasks that occur late in the project schedule. Most engineers are under tremendous time to market (TTM) pressure due to competition while being told that they must minimize the cost of both the project and the end chip. In addition, they are struggling to meet power, performance, and area (PPA) requirements far more aggressi... » read more

Improving Design Collaboration In The Age Of Remote Work
By Amit Varde - 13 Sep, 2022 - Comments: 0

Teams of analog and mixed signal (AMS) design and layout engineers spend countless hours extracting every ounce of performance out of their design. They continually make incremental changes daily to the design until the very end, as close to tape out as possible. Each change made to the design requires corresponding changes to the circuit layout. As technology advances, accounting for the paras... » read more

ECO Should Not Stand For Extended Challenge Order
By Manoj Chacko - 25 Aug, 2022 - Comments: 0

There’s an old saying that the first 90% of a task takes 90% of the schedule, and the remaining 10% takes the other 90% of the time. In chip development, design-signoff closure has become one such task. Ideally, when the design has been placed and routed (physical implementation), final analysis of timing and other metrics is performed and an engineering change order (ECO) file is issued to t... » read more

Overcoming The Growing Challenge Of Dynamic IR-Drop
By PV Srinivas - 24 Mar, 2022 - Comments: 0

IR-drop has always been somewhat of an issue in chip design; voltage decreases as current travels along any path with any resistance. Ohm’s Law is likely the first thing that every electrical engineer learns. But the challenges related to IR-drop (sometimes called voltage drop) have increased considerably in recent years, especially the dynamic IR-drop in the power/ground grid as circuits swi... » read more

3 Ways To Improve Design Collaboration: Part 2
By Amit Varde - 04 Jun, 2020 - Comments: 0

In the last blog in this series, we talked about how VDD can help design and layout engineers work more efficiently. Communicating precise and accurate information is a key factor in improving productivity, estimates, and the planning process. Visualizing the changes makes it easier to follow the technical details. The ECO (Engineering Change Order) phase is an important phase in the lifecycle... » read more

3 Ways To Improve Design Collaboration
By Amit Varde - 13 Apr, 2020 - Comments: 0

In my experience, design engineers are zealous folks who want to extract every ounce of performance out of their design. They continue to make incremental changes to the design until the very end, as close to tape out as possible. Each change made to the design requires corresponding changes to be implemented in the layout. If you are a design engineer, how do you answer this question from y... » read more

Visualizing Differences In Analog Design
By Ed Sperling - 11 Mar, 2020 - Comments: 0

Prathna Sekar, technical account manager at ClioSoft, explains the challenges of managing analog versus digital IP, including how to deal with dozens or even hundreds of versions of a schematic, and why visualization is so important for identifying changes and updates to an analog design. » read more

Visually Assisted Layout In Custom Design
By Ed Sperling - 29 Oct, 2019 - Comments: 0

Avina Verma, group director for R&D in Synopsys’ Design Group, explains why visual feedback and graphical guidance are so critical in complex layouts, particularly for mixed-signal environments. » read more

Regain Your Power With Machine Learning
By Shekhar Kapoor - 22 Feb, 2018 - Comments: 0

It wasn’t too long ago that machine learning (ML) seemed like a fascinating research topic. However, in no time at all, it has made a swift transition from a world far-off to common presence in news, billboards, workplaces, and homes. The concept itself is not new but evidently what has caused it to take off is the rapid growth of data in many applications and more computational power. Closer... » read more

ECO Fill Can Rescue Your SoC Tapeout Schedule
By Vikas Gupta - 16 Feb, 2017 - Comments: 0

By Vikas Gupta and Bhavani Prasad Integrated circuit (IC) design and manufacturing is one of the most challenging engineering industries. As soon as a design engineer gets into “the groove” and feels comfortable taping out in a particular technology node, the next technology node shrink is already there to pose a new and greater set of challenges. While it almost goes without saying that... » read more

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