Golden Signoff ECO For Last-Mile Electronic Design Closure

Timing convergence with fewer iterations and faster turnaround time.


Electronic design developers really hate iterative, resource-intensive tasks that occur late in the project schedule. Most engineers are under tremendous time to market (TTM) pressure due to competition while being told that they must minimize the cost of both the project and the end chip. In addition, they are struggling to meet power, performance, and area (PPA) requirements far more aggressive than previous product generations, driven by end markets such as data centers, mobile, automotive, artificial intelligence (AI), and the Internet of Things (IoT). Trying to optimize all these dimensions at the same time in the “last mile” of a long schedule is a huge challenge. Every iteration loop delays design closure, prolongs TTM, and may lead to compromises in meeting the requirements.

One area that traditionally has involved multiple long iterations is the process of timing closure. Back when designs were laid out by hand, unpleasant surprises were a given when timing analysis was run on the layout, and multiple manual iterations before tapeout were required. Automating the implementation process with logic synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing tools helped some, with even better results when these tools became timing aware. Today, they perform static timing analysis (STA) on the fly as the design is implemented. The goal is for the resulting layout to meet all timing requirements.

Unfortunately, most chip projects are not achieving this goal. At the conclusion of place and route, they run signoff STA and find both setup and hold time violations. The primary reason is that the types of analysis have increased due to the physical effects of advanced node silicon processes. In addition, many projects use different vendors and different tools for implementation and signoff STA, so the correlation is loose at best. Fixing the timing problems requires an engineering change order (ECO) tool to create a series of instructions for the implementation tools to tweak the layout to get better signoff STA results.

This is not a one-time pass. Typical chip projects can take around twenty ECO iterations to get enough convergence for signoff STA to match the predicted results. On large designs, each ECO run takes a few days and each layout run take a few days, so the TAT for each iteration is more than a week. The upshot is that many chip development teams spend at least a month, and often more, trying to achieve timing signoff. This has a huge impact on project cost and TTM. The industry clearly needs a more integrated ECO solution with both shorter TAT and fewer iterations for timing convergence.

Even with all its challenges, timing is just one aspect of design closure for modern chips. Historically, clock trees and leakage power have also required multiple ECO loops to achieve signoff status. Deep submicron process nodes have brought additional types of ECOs into the signoff loop, including dynamic power, reliability and IR drop, aging, process variations and robustness, post-mask metal rules, and various design rule checks.

A modern ECO solution must span all these dimensions, delivering fast TAT and enabling minimal iterations. It must be physically aware so that it can provide optimized instructions to the layout tools for predictable results and rapid convergence to signoff. It also must have high capacity, able to support the growing number of corners at which analysis is performed.

Synopsys PrimeClosure builds on the capabilities of Synopsys PT-ECO and Synopsys Tweaker, and adds new technologies for ECO. It has capacity for more than a hundred scenarios on designs, with more than a billion instances. It can process “dirty” designs with many violations efficiently and quickly, making it suitable for running as soon as preliminary layouts are available. Accurate timing and excellent timing correlation throughout the flow is provided by direct integration of Synopsys PrimeTime.

There are numerous dimensions of design optimization, closure, and signoff. Synopsys PrimeClosure focuses on resolving issues with timing, power, performance, area, clock network, voltage drop, robustness, variation, aging, and metal. Closure for robustness, parasitic variation, and aging is aided by tight integration with Synopsys PrimeShield, and voltage by tight integration with Ansys RedHawk-SC.

In addition, it can perform hierarchical ECO, reading top-level reports to run block-level ECO, and vice-versa. It provides a unified cockpit for all ECO activity, including support for versatile and interactive editing in all views (physical, schematic, netlist, etc.) Traditional ECO tools automate only about 85% to 90% of PPA optimization, and the remaining closure requires customized recipes, expert engineer knowledge, tedious manual tweaking, and months of iterations. Integrating the proven AI and machine learning (ML) flow of Synopsys massively scales exploration of last-mile design optimization. This replaces the traditional labor-intensive effort by automating less consequential decisions and achieving design targets in a fraction of the time and with fewer hardware resources. Find out more here.

Leave a Reply

(Note: This name will be displayed publicly)