3 Ways To Improve Design Collaboration: Part 2


In the last blog in this series, we talked about how VDD can help design and layout engineers work more efficiently. Communicating precise and accurate information is a key factor in improving productivity, estimates, and the planning process. Visualizing the changes makes it easier to follow the technical details. The ECO (Engineering Change Order) phase is an important phase in the lifecycle... » read more

3 Ways To Improve Design Collaboration


In my experience, design engineers are zealous folks who want to extract every ounce of performance out of their design. They continue to make incremental changes to the design until the very end, as close to tape out as possible. Each change made to the design requires corresponding changes to be implemented in the layout. If you are a design engineer, how do you answer this question from y... » read more

Visualizing Differences In Analog Design


Prathna Sekar, technical account manager at ClioSoft, explains the challenges of managing analog versus digital IP, including how to deal with dozens or even hundreds of versions of a schematic, and why visualization is so important for identifying changes and updates to an analog design. » read more

Visually Assisted Layout In Custom Design


Avina Verma, group director for R&D in Synopsys’ Design Group, explains why visual feedback and graphical guidance are so critical in complex layouts, particularly for mixed-signal environments. » read more

Regain Your Power With Machine Learning


It wasn’t too long ago that machine learning (ML) seemed like a fascinating research topic. However, in no time at all, it has made a swift transition from a world far-off to common presence in news, billboards, workplaces, and homes. The concept itself is not new but evidently what has caused it to take off is the rapid growth of data in many applications and more computational power. Closer... » read more

ECO Fill Can Rescue Your SoC Tapeout Schedule


By Vikas Gupta and Bhavani Prasad Integrated circuit (IC) design and manufacturing is one of the most challenging engineering industries. As soon as a design engineer gets into “the groove” and feels comfortable taping out in a particular technology node, the next technology node shrink is already there to pose a new and greater set of challenges. While it almost goes without saying that... » read more

The Fill Ecosystem Evolves Again


Several years ago, we wrote about the ecosystem of fill, and how 20nm technology required a much tighter relationship between the foundry, designers and EDA vendors. While the players remain the same, there have been some interesting shifts in fill techniques and usage as designers move to even-smaller technologies. What continues with each node is the additional complexity of the design flo... » read more

Pressure Builds To Revamp The Design Flow


Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

Incremental Design Methodologies


There are times when we become stuck in the past, or choose to believe something that is no longer true or actually never was true. As we get older, we are all guilty of that. History tends to rewrite itself, especially given that this industry is aging. One of these situations occurred recently, and comments from an industry luminary didn’t align with the thoughts and memories of other peopl... » read more