tag: EDA tools

Improving PPA With AI
By John Koon - 12 May, 2022 - Comments: 0

AI/ML/DL is starting to show up in EDA tools for a variety of steps in the semiconductor design flow, many of them aimed at improving performance, reducing power, and speeding time to market by catching errors that humans might overlook. It's unlikely that complex SoCs, or heterogeneous integration in advanced packages, ever will be perfect at first silicon. Still, the number of common error... » read more

Solution Efficiencies For Dynamic Function eXchange Using Abstract Shells
By Xilinx - 04 Aug, 2021 - Comments: 0

Dynamic Function eXchange (DFX) enables great flexibility within Xilinx® silicon, empowering you to load applications on demand, deliver updates to deployed systems, and reduce power consumption. Platform designs allow for collaboration between groups, where one group can focus on infrastructure and another on hardware acceleration. However, DFX has fundamental flow requirements that lead to l... » read more

RISC-V Challenges And Opportunities
By Ed Sperling - 24 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation. (L-... » read more

Baum: Finding SoC Power Flaws
By Kevin Fogarty - 28 Aug, 2018 - Comments: 0

A South Korean startup founded by a Samsung engineer-turned-researcher has created a tool that finds power design flaws early in the SoC design process. The startup, Baum, Inc., launched the second version of its power-modeling solution in June at DAC. The product is a power design-verification tool that uses high-level models to create analyses designed to spot design flaws that could creat... » read more

The “Last Simple Node” And the Internet of Things
By Brian Fuller - 17 Oct, 2013 - Comments: 0

Power, performance and size are key targets that will enable the expected explosion of the Internet of Things (IoT). Today, most observers see the path to that running directly through 16/14nm finFET and below for the node’s ability to manage power and size and boost integration. Geoff Lees isn’t your average observer. The vice president and general manager of Freescale’s microcon... » read more

Reflecting on the Future
By Ann Mutschler - 13 Jun, 2013 - Comments: 0

Since returning from the Design Automation Conference, I’ve been reflecting on some very interesting discussions I had last week in Austin. The ones that are sticking with me concern the old, sequential algorithms that run EDA tools today. The fact is, given design complexity, they are running out of steam. As a result, the industry is looking at possibly leveraging GPUs since they may be ... » read more

Experts At The Table: Pain Points
By Ed Sperling - 20 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: With stacked die it’s no longer one company making an SoC. W... » read more

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