Improving PPA With AI


AI/ML/DL is starting to show up in EDA tools for a variety of steps in the semiconductor design flow, many of them aimed at improving performance, reducing power, and speeding time to market by catching errors that humans might overlook. It's unlikely that complex SoCs, or heterogeneous integration in advanced packages, ever will be perfect at first silicon. Still, the number of common error... » read more

A Holistic Approach To Energy-Efficient System-On-Chip (SoC) Design


It takes a great deal of energy to power the modern world, and demand grows every day. This is especially true for electronics, where ever increasing automation and more intelligent devices incessantly demand more power. Many applications that use chips face a variety of pressures for reduced power consumption and better energy efficiency. In response, the semiconductor and electronic design au... » read more

CEO Outlook: Chip Industry 2022


Semiconductor Engineering sat down to discuss broad industry changes and how that affects chip design with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a live audience... » read more

Semiconductor Scaling Is Failing — What Next For Processors?


This in-depth paper looks at the changing dynamics in the semiconductor industry. In other words, why many companies are looking to customize their processor designs to keep pace with software and system demands. It goes onto highlight the opportunities available to companies of all sizes, in seeking to differentiate and specialize their processor designs. Click here to read more. » read more

Hardware-Supported Patching of Security Bugs in Hardware IP Blocks


New research paper from Duke University, University of Calgary, NYU & Intel. Abstract: "To satisfy various design requirements and application needs, designers integrate multiple Intellectual Property blocks (IPs) to produce a system-on-chip (SoC). For improved survivability, designers should be able to patch the SoC to mitigate potential security issues arising from hardware IPs; for incre... » read more

EDA On Cloud Presents Unique Challenges


Discussions about cloud-based EDA tools are heating up for both hardware and software engineering projects, opening the door to vast compute resources that can be scaled up and down as needed. Still, not everyone is on board with this shift, and even companies that use the cloud don't necessarily want to use it for every aspect of chip design. But the number of cloud-based EDA tools is growi... » read more

Autonomous Design Automation: How Far Are We?


The year is 2009, during the Design Automation Conference (DAC) at a press dinner in a posh little restaurant in San Francisco’s Civic Center. About two glasses of red wine in, one of the journalists challenges the table: “So, how far away are we from the black box that we feed with our design requirements and it produces the design that we send to the foundry?” We discussed all the indus... » read more

How To Justify A Data Center


The breadth of cloud capabilities and improvements in cost and licensing structures is prompting chipmakers to consider offloading at least some of their design work into the cloud. Cloud is a viable business today for semiconductor design. Over the past decade, the interest in moving to cloud computing has grown from an idea that was fun to talk about — but which no one was serious about ... » read more

Planning EDA’s Next Steps


Anirudh Devgan, Cadence's new CEO, and the recipient of the Phil Kaufman Award in December, sat down with Semiconductor Engineering to talk about what's next in EDA, the underlying technology and business challenges and changes, and new markets that are unfolding for floor-planning, verification, CFD, and advanced packaging. SE: Where does EDA need to improve? Devgan: We have made it much... » read more

Preparing For Test Early In The Design Flow


Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

← Older posts Newer posts →