tag: EDA

No More Straight Lines
By Ed Sperling - 12 May, 2016 - Comments: 0

Shrinking features on a chip is no longer the only way forward, and in an increasing number of designs and markets, it is no longer the best way forward. Power and performance are generally better dealt with using different architectures and microarchitectures, and all of those provide the potential to reduce silicon area (cost). Cramming more transistors on a die and working around leakage... » read more

IP Business Models In Flux
By Ann Mutschler - 12 May, 2016 - Comments: 0

EDA and IP suppliers are engaging with foundries earlier with each manufacturing process node, while those foundries are providing ever more optimized and tuned processes to their customers. As part of this, IP providers must port their IP offerings to the various foundries and processes, putting a squeeze on resources. That raises some difficult questions, such as how to prioritize their li... » read more

Addressing The Challenges Of Photonic IC Design Via An Integrated Electronic/Photonic Design Automation Environment
By Cadence - 11 May, 2016 - Comments: 0

Photonics—the science and technology of generating, controlling, and detecting light—is transitioning quickly into mainstream electronic designs. Photonic IC (PIC) design does, however, come with some unique challenges in areas including layout, error checking, and circuit modeling. While electronic designers would have expertise in using a traditional electronic design automation (EDA) flo... » read more

Automating System Design
By Ann Mutschler - 02 May, 2016 - Comments: 1

Change is underway in the chip design world, creating opportunities and challenges that reach far beyond questions about whether Moore’s Law is slowing or stopping. Never before in the history of semiconductors has design been so complex and sophisticated, and never has it touched so many lives in so many interesting ways. This is all happening as a result of the chip’s enabling role in ... » read more

ESL Flow is Dead
By Brian Bailey - 28 Apr, 2016 - Comments: 3

It was 20 years ago that Gary Smith coined the term [getkc id="48" comment="Electronic System Level"] (ESL). He foresaw the next logical migration in abstraction up from the [getkc id="49" comment="Register Transfer Level"] (RTL) to something that would be capable of describing and building complex electronic systems. He also saw that the future of EDA depended upon who would control that marke... » read more

Analyzing The Integrity Of Power
By Ann Mutschler - 14 Apr, 2016 - Comments: 0

Power analysis is shifting much earlier in the chip design process, with power emerging as the top design constraint at advanced process nodes. As engineering teams pack more functionality and content into bigger and more complex chips, they are having to deal with more complex interactions that affect everything from power to its impact on signal integrity and long-term reliability. That, i... » read more

EDAC Changes Name
By Ed Sperling - 31 Mar, 2016 - Comments: 1

The EDA Consortium today changed its name to the Electronic System Design Alliance, a move that expands the group's charter to reflect shifts that have been underway in the chip design world for some time. Those shifts include the growth in IP and an increased focus on software development. Classic EDA, from place and route to synthesis to back-end debug and verification, are still very much... » read more

EDA Sales Down Slightly
By Ed Sperling - 24 Mar, 2016 - Comments: 0

EDA sales dropped 1.9% in Q4 of 2015, following a spectacular run of 23 consecutive quarters of solid growth. For the year, the EDA and IP industry posted 5% growth. It's hard to read too much into a single quarter, especially when growth for the full year was up 5%, according to numbers released by the EDA Consortium's Market Statistics Service. Computer-aided engineering (CAE), the largest... » read more

What’s Next for System-Level Power Modeling?
By Alan Gibbons - 23 Mar, 2016 - Comments: 1

Availability of models and libraries has long been one of the biggest barriers to the adoption of new EDA tools and methodologies, whether due to the investment needed to create these models and libraries or because of the “at-risk” nature of developing complex models in proprietary formats. With the approval of UPF3.0 (IEEE 1801-2015) this past December, we now have an industry standar... » read more

Inside The OSAT Business
By Mark LaPedus - 17 Mar, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the IC-packaging industry, foundries, China and other topics with Tien Wu, chief operating officer at Taiwan's Advanced Semiconductor Engineering (ASE), the world's largest outsourced semiconductor assembly and test (OSAT) vendor. What follows are excerpts of that conversation. SE: What is your overall outlook for 2016? Wu: Last year, the semi... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy