tag: edge

Challenges Of Edge AI Inference
By Vinay Mehta - 01 Jul, 2021 - Comments: 0

Bringing convolutional neural networks (CNNs) to your industry—whether it be medical imaging, robotics, or some other vision application entirely—has the potential to enable new functionalities and reduce the compute requirements for existing workloads. This is because a single CNN can replace more computationally expensive image processing, denoising, and object detection algorithms. Howev... » read more

Challenges In Developing A New Inferencing Chip
By Ed Sperling - 01 Jul, 2021 - Comments: 0

Cheng Wang, co-founder and senior vice president of software and engineering at Flex Logix, sat down with Semiconductor Engineering to explain the process of bringing an inferencing accelerator chip to market, from bring-up, programming and partitioning to tradeoffs involving speed and customization.   SE: Edge inferencing chips are just starting to come to market. What challenges di... » read more

ACAP At The Edge With The Versal AI Edge Series
By Xilinx - 30 Jun, 2021 - Comments: 0

This white paper introduces the AI Edge series to the Versal ACAP portfolio, a domain-specific architecture (DSA) that meets the strenuous demands of systems implemented in the 7nm silicon process. This series is optimized to meet the performance-per-watt requirements of edge nodes at or near the analog-digital boundary. Here, immediate response to the physical world is highly valued, and in ma... » read more

Architectural Considerations For AI
By Brian Bailey - 24 Jun, 2021 - Comments: 2

Custom chips, labeled as artificial intelligence (AI) or machine learning (ML), are appearing on a weekly basis, each claiming to be 10X faster than existing devices or consume 1/10 the power. Whether that is enough to dethrone existing architectures, such as GPUs and FPGAs, or whether they will survive alongside those architectures isn't clear yet. The problem, or the opportunity, is that t... » read more

Customizing Chips For Power And Performance
By Ed Sperling - 10 Jun, 2021 - Comments: 0

Sandro Cerato, senior vice president and CTO of the Power & Sensor Systems Business Unit at Infineon Technologies, sat down with Semiconductor Engineering to talk about fundamental shifts in chip design with the rollout of the edge, AI, and more customized solutions. What follows are excerpts of that conversation. SE: The chip market is starting to fall into three distinct buckets, the e... » read more

Configuring AI Chips
By Ed Sperling - 04 Jun, 2021 - Comments: 0

Change is almost constant in AI systems. Vinay Mehta, technical product marketing manager at Flex Logix, talks about the need for flexible architectures to deal with continual modifications in algorithms, more complex convolutions, and unforeseen system interactions, as well as the ability to apply all of this over longer chip lifetimes. Related Dynamically Reconfiguring Logic A differ... » read more

Hyperconnectivity, Hyperscale Computing, And Moving Edges
By Frank Schirrmeister - 27 May, 2021 - Comments: 0

As described in “The Four Pillars of Hyperscale Computing” last year, the four core components that development teams consider for data centers are computing, storage, memory, and networking. Over the previous decade, requirements for programmability have fundamentally changed data centers. Just over a decade ago, in 2010, virtual machines would compute user workloads on CPU-centric archite... » read more

Kria K26 SOM: The Ideal Platform For Vision AI At The Edge
By Xilinx - 12 May, 2021 - Comments: 0

With various advancements in artificial intelligence (AI) and machine learning (ML) algorithms, many high-compute applications are now getting deployed on edge devices. So, there is a need for an efficient hardware that can execute complex algorithms efficiently as well as adapt to rapid enhancements in this technology. Xilinx's Kria K26 SOM is designed to address the requirements of executing ... » read more

Why Reconfigurability Is Essential For AI Edge Inference Throughput
By Vinay Mehta - 06 May, 2021 - Comments: 0

For a neural network to run at its fastest, the underlying hardware must run efficiently on all layers. Through the inference of any CNN—whether it be based on an architecture such as YOLO, ResNet, or Inception—the workload regularly shifts from being bottlenecked by memory to being bottlenecked by compute resources. You can think of each convolutional layer as its own mini-workload, and so... » read more

IC Security Threat Grows As More Devices Are Connected
By Ann Mutschler - 06 May, 2021 - Comments: 0

Designing for security is beginning to gain traction across a wider swath of chips and systems as more of them are connected to the Internet and to each other, sometimes in safety- and mission-critical markets where the impact of a cyber attack can be devastating. But it's also becoming more difficult to design security into these systems. Unlike in the past, connectivity is now considered e... » read more

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