Accelerate Custom Layout Using Custom Compiler’s User-Defined Device (UDD)

In this 7th video of the series, Kai Wang, Director of Engineering at Synopsys, discusses in-design electrical analysis, and why it is critical to use signoff engines to check and fix resistance, capacitance and electromigration issues during layout. Click here to access this video whitepaper. » read more

System-Level, Post-Layout Electrical Analysis For High-Density Advanced Packaging

As HDAP designs become more popular, the need for post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification (DRC and LVS) is growing. Mentor provides an accurate, automated flow that generates the required HDAP netlist for simulation/STA to enable HDAP designers to ensure that the HDAP will perform as designed. To read more, click here. » read more