tag: electrostatic discharge

Transient Power Problems Rising
By Ann Mutschler - 08 Jun, 2017 - Comments: 0

Transient power is becoming much more problematic at 10/7nm, adding yet another level of complexity for design teams already wrestling with power issues caused by leakage, a variety of power management techniques to control dynamic power, and leakage current. At each new node there is less headroom for engineering teams to address these problems, and more likelihood that what they do in one ... » read more

Assessing ESD Sensitivity Of Interface IP Using Charged Device Model
By Synopsys - 07 Dec, 2016 - Comments: 0

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, especially from the completion of the silicon wafer processing to when the device is assembled in the system. The most commonly used ESD test models are the Human Body Model (HBM) and the Charged Device Model (CDM). Both models assess the ESD sensitivity of a device, however due to the rapi... » read more

7nm Design Success Starts With Multi-Domain Multi-Physics Analysis
By Arvind Vel - 28 Nov, 2016 - Comments: 1

Companies can benefit from advancements in the latest semiconductor process technology by delivering smaller, faster and lower power products, especially for those servicing mobile, high performance computing and automotive ADAS applications. By using 7nm processes, design teams are able to add a lot more functionality onto a single chip and lower the power consumption by scaling operating volt... » read more

Why Do You Need Chip-Package-System Co-Design And Co-Analysis?
By Youngsoo Lee - 13 Oct, 2016 - Comments: 0

Whether it is the need for sustainable energy, or driving performance while keeping power at bay, or enabling safe and reliable operation of any electronic system, containment of electronic noise — power and signal noise is critical to all of the above. Other factors that impact safe and reliable operation are electromigration (EM), electromagnetic interference (EMI) and mechanical stress ena... » read more

Rethinking Memory
By Ed Sperling - 16 Dec, 2015 - Comments: 3

Getting data in and out of memory is as important as the speed and efficiency of a processor, but for years design teams managed to skirt the issue because it was quicker, easier and less expensive to boost processor clock frequencies with a brute-force approach. That worked well enough prior to 90nm, and adding more cores at lower clock speeds filled the gap starting at 65nm. After that, th... » read more

System-Aware Full-Chip Power Integrity And Reliability
By Calvin Chew - 12 Nov, 2015 - Comments: 0

At the core of every electronics system is a chip that has to meet multiple conflicting requirements such as increased functionality, best power efficiency, highest reliability, lowest design cost and short design schedule. Meeting these requirements poses a major challenge, especially for systems on chip (SoCs) that are designed using advanced processes. Ensuring that the SoCs meet power an... » read more

Stacked Die, Phase Two
By Ed Sperling - 09 Apr, 2015 - Comments: 0

The initial hype phase of [getkc id="82" kc_name="2.5D"] appears to be over. There are multiple offerings in development or on the market already from Xilinx, Altera, Cisco, Huawei, IBM, AMD, all focused on better throughput over shorter distances with better yield and lower power. Even Intel has jumped on the bandwagon, saying that 2.5D will be essential for extending [getkc id="74" comment="M... » read more

Optimizing Analog For Power At Advanced Nodes
By Ann Mutschler - 09 Oct, 2014 - Comments: 0

As any engineering manager will tell you, analog and digital engineers seem like they could be from different planets. While this has changed somewhat over time, [getkc id="52" comment="analog"] is still something of a mystery to many in [getkc id="81" kc_name="SoC"] design teams. Throw power management into the mix and things really get interesting. Improvements in analog/mixed-signal tools... » read more

FinFET Based Designs: Reliability Verification Implications
By Aveek Sarkar - 10 Jul, 2014 - Comments: 1

Over the past few months, I’ve discussed various challenges associated with finFET-based designs. We all know that finFET devices enable design teams to operate their chips at significantly lower supply voltages with a very tight control on leakage current. But to control the overall power within a tight power budget, the challenge shifts to how the logic design is managed such that the overa... » read more

FinFET Based Designs: Power Analysis Considerations
By Aveek Sarkar - 10 Apr, 2014 - Comments: 2

Design teams working on mobile, computing, networking and other low power, high performance IPs and SoCs are migrating to FinFET-based technologies. However the benefits from their smaller sizes and the ability to deliver consistent performance at ultra-low sub-1V nominal supply voltage levels is outweighed by the worsening of power noise and reliability. As mentioned in an earlier blog on Powe... » read more

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