tag: Eliyan

UMI Can Scale the Memory Wall
By Eliyan - 25 Sep, 2024 - Comments: 0

While the improvements in processor performance to enable the incredible compute requirements of applications like Chat-GPT get all the headlines, a not-so-new phenomenon known as the memory wall risks negating those advancements. Indeed, it has been clearly demonstrated that as CPU/GPU performance increases, wait time for memory also increases, preventing full utilization of the processors. ... » read more

Simultaneous Bi-Directional Signaling: A Breakthrough Alternative For Multi-Die Assemblies
By Ramin Farjadrad - 29 Aug, 2024 - Comments: 0

In designing multi-die systems-in-package, with or without chiplets, it is easy to think of the interconnect between dies as simply analogous to the interconnect between functional blocks on a single die. But this analogy can lead architects and designers into a blind alley from which it becomes impossible to meet system performance and power requirements. The reason lies in fundamental differe... » read more

Chiplets and the Early Adopter’s Dilemma
By Eliyan - 28 Aug, 2024 - Comments: 0

Early adopters of a new technology often face a serious dilemma. On one hand, moving early means exploiting the most aggressive new technology available. But on the other hand, making early technology decisions can lock a product line into a path that will later become uncompetitive—either a single-vendor solution that can’t guarantee continuity of supply, or a roadmap that can’t shift an... » read more

Chip Industry Week In Review
By The SE Staff - 16 Aug, 2024 - Comments: 0

The U.S. Department of Commerce and Texas Instruments (TI) signed a non-binding preliminary memorandum of terms to provide up to $1.6 billion in CHIPS Act funding towards TI’s investment of over $18 billion for three 300mm semiconductor wafer fabs under construction in Texas and Utah. TI also expects to get about $6 billion to $8 billion from the U.S. Department of Treasury’s Investmen... » read more

What’s Missing In 2.5D EDA Tools
By Brian Bailey - 28 Mar, 2024 - Comments: 0

Gaps in EDA tool chains for 2.5D designs are limiting the adoption of this advanced packaging approach, which so far has been largely confined to high-performance computing. But as the rest of the chip industry begins migrating toward advanced packaging and chiplets, the EDA industry is starting to change direction. There are learning periods with all new technologies, and 2.5D advanced pack... » read more

2.5D Integration: Big Chip Or Small PCB?
By Brian Bailey - 29 Feb, 2024 - Comments: 1

Defining whether a 2.5D device is a printed circuit board shrunk down to fit into a package, or is a chip that extends beyond the limits of a single die, may seem like hair-splitting semantics, but it can have significant consequences for the overall success of a design. Planar chips always have been limited by size of the reticle, which is about 858mm2. Beyond that, yield issues make the si... » read more

Chip Industry Week In Review
By The SE Staff - 09 Feb, 2024 - Comments: 0

By Jesse Allen, Linda Christensen, and Liz Allan.  The Biden administration plans to invest more than $5B  for semiconductor R&D and workforce support, including in the National Semiconductor Technology Center (NSTC), as part of the rollout of the CHIPS Act. Today's announcement included at least hundreds of millions for the NSTC workforce efforts, including creating a Workforce Cente... » read more

Chiplets: Deep Dive Into Designing, Manufacturing, And Testing
By The SE Staff - 07 Aug, 2023 - Comments: 0

Chiplets are a disruptive technology. They change the way chips are designed, manufactured, tested, packaged, as well as the underlying business relationships and fundamentals. But they also open the door to vast new opportunities for existing chipmakers and startups to create highly customized components and systems for specific use cases and market segments. This LEGO-like approach sounds ... » read more

Mini-Consortia Forming Around Chiplets
By Ed Sperling - 20 Mar, 2023 - Comments: 0

Mini-consortia for chiplets are sprouting up across the industry, driven by demands for increasing customization in tight market windows and fueled by combinations of hardened IP that have been proven in silicon. These loosely aligned partnerships are working to develop LEGO-like integration models for highly specific applications and end markets. But they all are starting small, because it'... » read more

Panel Tackles Chiplet Packaging Challenges
By QP Technologies Staff - 16 Mar, 2023 - Comments: 1

QP Technologies recently exhibited at the first Chiplet Summit, held January 24-26 in San Jose, California. Dick Otte, CEO of our parent company Promex Industries, participated on a panel titled “Best Packaging for Chiplets Today.” Moderated by Nobuki Islam with JCET Group, the packaging panel also included Daniel Lambalot, Alphawave Semi; Laura Mirkarimi, Adeia; Syrus Ziai, Eliyan; and Mik... » read more

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