Neural Architecture & Hardware Accelerator Co-Design Framework (Princeton/ Stanford)


A new technical paper titled "CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework" was published by researchers at Princeton University and Stanford University. "Recently, automated co-design of machine learning (ML) models and accelerator architectures has attracted significant attention from both the industry and academia. However, most co-design frameworks either... » read more

Embedded Multicore: Enablement Of Heterogeneous OSes And Mixed Criticality Systems


The implementation of multicore embedded systems is becoming increasingly common. The decision to realize a design using multiple processors may be influenced by a number of factors; broadly these are technical goals to attain, a time to market to achieve, and target design and production costs. Using multicore in a design requires a number of key decisions, which, as with most embedded systems... » read more