System-Aware Full-Chip Power Integrity And Reliability


At the core of every electronics system is a chip that has to meet multiple conflicting requirements such as increased functionality, best power efficiency, highest reliability, lowest design cost and short design schedule. Meeting these requirements poses a major challenge, especially for systems on chip (SoCs) that are designed using advanced processes. Ensuring that the SoCs meet power an... » read more

New System Requirements Demand a Creatively Choreographed Ecosystem


In the past, integrated circuits, packages and boards were all designed independently, and yet in most cases still managed to fit together with very few functional or technical problems. However, recent advances in chip performance have changed this process dramatically. New designs, processes and materials already have been seen in packaging as high-performance semiconductor chips need to c... » read more

Executive Insight: Wally Rhines


Wally Rhines, chairman and CEO of Mentor Graphics, sat down with Semiconductor Engineering to talk about what's changing across a wide swath of the industry, where the new opportunities will be, when security will become a real opportunity for EDA, and why Moore's Law will die but progress will continue forever. SE: Looking back over the past year, what's changed and where are the possible r... » read more

How Switching Activity Impacts A Design’s Power And Reliability


Electronics continue to gain presence in both familiar and unfamiliar areas of our lives. Electronics is a common thread among the cars we drive, the computers we use, the mobile phones and wearable devices that we rely on. We appreciate the information and convenience that Fitbits and other products such as coffee makers, credit cards and building security cards provide us. And we are beginni... » read more

Tools And Flows In 2015


This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

Executive Briefing: Andrew Yang


By Ed Sperling Andrew Yang, president of ANSYS subsidiary Apache Design, sat down with Low-Power/High-Performance Engineering to talk about why power is becoming so important and where the future challenges lie. What follows are excerpts of that conversation. LPHP: What’s the most important issue these days for chipmakers? Yang: According to the feedback we’ve gotten from our customer... » read more

The Power Problem


For the past few years, EDA companies have been warning chipmakers that power will become the biggest issue they face at future nodes. They were right. While it may not be the only big problem—after all, the number of issues at each new tick of Moore’s Law is growing—power is certainly one of the most challenging and by far the most pervasive. In fact, the warnings about just how perni... » read more

Challenges In IC And Electronic Systems Verification


Power efficiency, unrealistic schedules, and cost-down considerations are increasingly the top challenges design teams must meet to deliver next generation electronic systems, whether it is for the mobile, server, or automotive market. In addition, a successful chip tapeout does not guarantee the eventual end-product’s success—there are many variables to take into account. In the first p... » read more

Dangerous Electricity


By Ann Steffora Mutschler Electricity to the modern age is as indispensible as air, but too much can be a bad thing for automotive and aerospace applications—especially when it is in the form of electrostatic discharge (ESD). As chips advance to 28nm, 20nm and 16nm, the design window for electrostatic discharge is shrinking for a number of reasons, explained Norman Chang is vice presi... » read more

Good Times For Analog Designers


By Ann Steffora Mutschler For a number of technological reasons, analog/mixed-signal design and low-power design are converging, and with that comes both challenges and opportunities. As far as challenges go, process variations at 14nm, 20nm and even 28nm have increased significantly to include DFM impacts such as layout-delay effects. On the digital side, those process changes affect... » read more

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